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參數(shù)資料
| 型號： | TSA5522T |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | XO, clock |
| 英文描述： | 1.4 GHz I2C-bus controlled synthesizer |
| 中文描述： | PLL FREQUENCY SYNTHESIZER, 1400 MHz, PDSO16 |
| 封裝： | 3.90 MM, PLASTIC, MS-012AC, SOT-109-1, SOP-16 |
| 文件頁數(shù)： | 7/20頁 |
| 文件大?。?/td> | 172K |
| 代理商： | TSA5522T |
1996 Jan 23
7
Philips Semiconductors
Product specification
1.4 GHz I
2
C-bus controlled synthesizer
TSA5522
Table 3
Address selection
Table 4
Test bits
Table 5
Ratio select bits
Table 6
Band switch output levels
VOLTAGE APPLIED ON AS
INPUT
MA1
MA2
0 to 0.1V
CC1
Always valid
0.4V
CC1
to 0.6V
CC1
0.9V
CC1
to V
CC1
0
0
1
1
0
1
0
1
T2
T1
T0
DEVICE OPERATION
0
0
1
1
1
1
0
1
1
1
0
0
1
X
0
1
0
1
normal mode
charge-pump is OFF
charge-pump is sinking current
charge-pump is sourcing current
f
ref
is available at LOCK output
1
2
f
div
is available at LOCK output
RSA
RSB
REFERENCE DIVIDER
X
0
1
0
1
1
640
1024
512
P2
P1
P0
VOLTAGE
ON BS
OUTPUT
PHILIPS M/O
BAND
0
1
0
1
0
0
0
0
1
0.25 V
0.4V
CC1
0.8V
CC1
band A
band B
band C
R
EAD MODE
; R/W = 1 (see Table 7)
Data can be read from the device by setting the R/W bit to
logic 1. After the slave address has been recognized, the
device generates an acknowledge pulse and the first data
byte (status byte) is transferred on the SDA line (MSB
first). Data is valid on the SDA line during a HIGH level of
the SCL clock signal. A second data byte can be read from
the device if the microcontroller generates an
acknowledge on the SDA line (master acknowledge). End
of transmission will occur if no master acknowledge
occurs. The device will then release the data line to allow
the microcontroller to generate a STOP condition. When
ports P4 to P7 are used as inputs, the corresponding bits
must
be logic 0 (high impedance state). The POR flag is
set to logic 1 at power-on. The flag is reset when an
end-of-data is detected by the device (end of a read
sequence). Control of the loop is made possible with the
in-lock flag (FL) which indicates when the loop is locked
(FL = 1).
The bits I2, to I0 represent the status of the I/O ports
P7, P5 and P4 respectively. A logic 0 indicates a LOW
level and a logic 1 indicates a HIGH level
(see “Characteristics”).
A built-in ADC is available at pin P6. This converter can be
used to apply AFC information to the microcontroller from
the IF section of the television. The relationship between
the bits A2 to A0 is given in Table 8.
Table 7
READ data format
Notes
1.
2.
3.
4.
5.
A = acknowledge.
POR = power-on-reset (POR = 1 at power-on).
FL = in-lock flag (FL = 1 when loop is locked).
I2 to I0 = digital levels for I/O ports P7, P5 and P4 respectively.
A2 to A0 = digital outputs of the 5-level ADC.
BYTE
MSB
DATA BYTE
LSB
COMMAND
A
(1)
Address byte (ADB)
Status byte (SB)
1
1
0
0
0
MA1
A2
(5)
MA0
A1
(5)
1
POR
(2)
FL
(3)
I2
(4)
I1
(4)
I0
(4)
A0
(5)
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