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參數(shù)資料
| 型號： | TSA5527M |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | XO, clock |
| 英文描述： | 1.3 GHz universal bus-controlled TV synthesizers |
| 中文描述： | PLL FREQUENCY SYNTHESIZER, 1300 MHz, PDSO16 |
| 封裝： | 4.40 MM, PLASTIC, SSOP-16 |
| 文件頁數(shù)： | 6/28頁 |
| 文件大小： | 290K |
| 代理商： | TSA5527M |
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1996 Sep 24
6
Philips Semiconductors
Product specification
1.3 GHz universal bus-controlled
TV synthesizers
TSA5526; TSA5527
PINNING
SYMBOL
PIN
DESCRIPTION
RF
V
EE
V
CC1
V
CC2
BS4
BS3
BS2
BS1
CP
V
tune
SW
1
2
3
4
5
6
7
8
9
10
11
RF signal input
ground
supply voltage (+5 V)
band switch supply voltage (+12 V)
PNP band switch buffer output 4
PNP band switch buffer output 3
PNP band switch buffer output 2
PNP band switch buffer output 1
charge-pump output
tuning voltage output
bus format selection input, I
2
C-bus
or 3-wire
lock detector output (3-wire bus/
ADC input (I
2
C-bus)
serial clock input
serial data input/output
chip enable/address selection input
crystal oscillator input
LOCK/ADC
12
SCL
SDA
CE
XTAL
13
14
15
16
Fig.2 Pin configuration.
handbook, halfpage
TSA5526
TSA5527
MBE326
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
RF
V
V
V
BS4
BS3
BS2
BS1
CP
SW
LOCK/ADC
SCL
SDA
CE
XTAL
EE
CC1
CC2
Vtune
FUNCTIONAL DESCRIPTION
The device is controlled via the I
2
C-bus or the 3-wire bus
depending on the voltage applied to the SW input (pin 11).
A HIGH level on the SW input enables the 3-wire bus
inputs which are CE (Chip Enable), SDA (serial data input)
and SCL (serial clock input). A LOW level on the SW input
enables the I
2
C-bus inputs which are AS (Address
Selection input), SDA (serial data input/output) and SCL
(serial clock input). The bus format selection is given in
Table 2.
I
2
C-bus mode (SW = LOW);
see Table 3
W
RITE MODE
(R/W = 0)
Data bytes can be sent to the device after the address
transmission (first byte). Four data bytes are required to
fully program the device. The bus transceiver has an
auto-increment facility which permits the programming of
the device within one single transmission
(address + 4 data bytes).
The device can also be partially programmed providing
that the first data byte following the address is Divider
Byte 1 (DB1) or the Control Byte (CB). The bits in the data
bytes are defined in Table 3.
The first bit of the first data byte transmitted indicates
whether frequency data (first bit = logic 0) or control and
band switch data (first bit = logic 1) will follow. Until an
I
2
C-bus STOP command is sent by the controller,
additional data bytes can be entered without the need to
readdress the device. The frequency register is loaded
after the 8th clock pulse of the second Divider Byte (DB2),
the control register is loaded after the 8th clock pulse of the
Control Byte (CB) and the band switch register is loaded
after the 8th clock pulse of the Band switch Byte (BB).
I
2
C-
BUS ADDRESS SELECTION
The module address contains programmable address bits
(MA1 and MA0) which offer the possibility of having
several synthesizers (up to 3) in one system by applying a
specific voltage to the CE input.
The relationship between MA1 and MA0 and the input
voltage applied to the CE input is given in Table 5.
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| TSA5526AT | ELECTRICAL POWER CORD |
| TSA5526M | ELECTRICAL POWER CORD |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| TSA5527T | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:1.3 GHz universal bus-controlled TV synthesizers |
| TSA5888 | 制造商:TSC 制造商全稱:Taiwan Semiconductor Company, Ltd 功能描述:Low Vcesat PNP Transistor High allowable power dissipation. |
| TSA5888CY RMG | 功能描述:兩極晶體管 - BJT PNP Transistor RoHS:否 制造商:STMicroelectronics 配置: 晶體管極性:PNP 集電極—基極電壓 VCBO: 集電極—發(fā)射極最大電壓 VCEO:- 40 V 發(fā)射極 - 基極電壓 VEBO:- 6 V 集電極—射極飽和電壓: 最大直流電集電極電流: 增益帶寬產(chǎn)品fT: 直流集電極/Base Gain hfe Min:100 A 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PowerFLAT 2 x 2 |
| TSA-5A | 制造商:OPTIFUSE 功能描述: |
| TSA6 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:EURO TERMINAL BLOCKS |
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