參數(shù)資料
型號(hào)： TSC2100IRHBG4
廠商： TEXAS INSTRUMENTS INC
元件分類： 消費(fèi)家電
英文描述： SPECIALTY CONSUMER CIRCUIT, PQCC32
封裝： 5 X 5 MM, GREEN, PLASTIC, QFN-32
文件頁數(shù)： 25/77頁
文件大小： 1079K
代理商： TSC2100IRHBG4
TSC2100
SLAS378 NOVEMBER 2003
www.ti.com
31
Interpolation Filter
The interpolation filter upsamples the output of the digital audio processing block by the required oversampling ratio. It
provides a linear phase output with a group delay of 21/Fs.
In addition, programmable digital interpolation filtering is included to provide enhanced image filtering and reduce signal
images caused by the upsampling process that are below 20 kHz. For example, upsampling an 8-kHz signal produces
signal images at multiples of 8 kHz (i.e., 8 kHz, 16 kHz, 24 kHz, etc). The images at 8 kHz and 16 kHz are below 20 kHz
and still audible to the listener; therefore, they must be filtered heavily to maintain a good quality output. The interpolation
filter is designed to maintain at least 65-dB rejection of images that land below 7.455 Fs. In order to utilize the programmable
interpolation capability, the Fsref should be programmed to a higher rate (restricted to be in the range of 39 kHz to 53 kHz
when the PLL is in use), and the actual Fs is set using the dividers in BITD5D3/REG00H/Page2. For example, if Fs
= 8 kHz is required, then Fsref can be set to 48 kHz, and the DAC Fs set to Fsref/6. This ensures that all images of the
8-kHz data are sufficiently attenuated well beyond a 20-kHz audible frequency range.
Delta-Sigma DAC
The audio digital-to-analog converter incorporates a third order multibit delta-sigma modulator followed by an analog
reconstruction filter. The DAC provides high-resolution, low-noise performance, using oversampling and noise shaping
techniques. The analog reconstruction filter design consists of a 6 tap analog FIR filter followed by a continuous time RC
filter. The analog FIR operates at a rate of 128 x Fsref (6.144 MHz when Fsref = 48 kHz, 5.6448 MHz when Fsref = 44.1 kHz).
Note that the DAC analog performance may be degraded by excessive clock jitter on the MCLK input. Therefore, care must
be taken to keep jitter on this clock to a minimum.
DAC Digital Volume Control
The DAC has a digital volume control block, which implements programmable gain. The volume level can be varied from
0dB to –63.5 dB in 0.5 dB steps, in addition to a mute bit, independently for each channel. The volume level of both channels
can also be changed simultaneously by the master volume control. The gain is implemented with a soft-stepping algorithm,
which only changes the actual volume by one step per input sample, either up or down, until the desired volume is reached.
The rate of soft-stepping can be slowed to one step per two input samples through bit D1 of control register 04H/Page2.
Because of soft-stepping, the host does not know when the DAC has been actually muted. This may be important if the
host wishes to mute the DAC before making a significant change, such as changing sample rates. In order to help with this
situation, the TSC2100 provides a flag back to the host via a read-only register bit (D2D3 of control register 04H/Page2)
that alerts the host when the part has completed the soft-stepping and the actual volume has reached the desired volume
level. The soft-stepping feature can be disabled by programming D14=1 in register 1DH in Page02. If soft-stepping is
enabled, the MCLK signal should be kept applied to the device until the DAC power-down flag is set. When this flag is set,
the internal soft-stepping process and power down sequence is complete, and the MCLK can be stopped if desired.
The TSC2100 also includes functionality to detect when the user switches on or off the de-emphasis or digital audio
processing functions, to first (1) soft-mute the DAC volume control, (2) change the operation of the digital effects
processing, and (3) soft-unmute the part. This avoids any possible pop/clicks in the audio output due to instantaneous
changes in the filtering. A similar algorithm is used when first powering up or down the DAC. The circuit begins operation
at power up with the volume control muted, then soft-steps it up to the desired volume level. At power down, the logic first
soft-steps the volume down to a mute level, then powers down the circuitry.
DAC Powerdown
The DAC powerdown flag ( D6 of REG05H/Page2) along with D10 of REG05H/Page2 denotes the powerdown status of
the DAC according to Table 4.
Table 4. DAC Powerdown Status
[D10,D6]
POWERUP / DOWN STATE OF DAC
[0,0]
DAC is in stable powerup state
[0,1]
DAC is in the process of powering up. The length of this state is determined by PLL and output driver
powerup delays controlled by register programming.
[1,0]
DAC is in the process of powering down. The length of this state is determined by soft-stepping of volume
control block and DAC pop reduction sequencing controlled by register programming.
[1,1]
DAC is in a stable powerdown state.
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