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TSC2100
SLAS378 NOVEMBER 2003
www.ti.com
56
REGISTER 1EH: Audio Control 5
BIT
NAME
READ/
WRITE
RESET
VALUE
FUNCTION
D15D9
MAX_AGC_PGA
R/W
1111111
MAX ADC PGA applicable for AGC
0000000 => 0 dB
0000001 => 0.5 dB
0000010 => 1.0 dB
1110110 => 59.0 dB
1110111 => 59.5 dB
1111000 => 59.5 dB
1111111 => 59.5 dB
D8D6
AGC_NOI_DEB
R/W
000
AGC Debounce time for speech mode to silence mode transition
000 => 0 ms
001 => 0.5 ms
010 => 1.0 ms
110 => 16.0 ms
111 => 32.0 ms
D5D3
AGC_SIG_DEB
R/W
000
AGC Debounce time for silence mode to speech mode transition
000 => 0 ms
001 => 0.5 ms
010 => 1.0 ms
110 => 16.0 ms
111 => 32.0 ms
D2
DRV_POP_DIS
R/W
0
Audio Output Driver POP reduction enable
0 => Enabled
1 => Disabled
D1
DRV_POP_LEN
R/W
0
Audio Output Driver POP reduction duration
0 => Output driver ramps to final voltage in approximately 1 msec, if VGND is
powered (0.8 sec otherwise)
1 => Output driver ramps to final voltage in approximately 5 msec, if VGND is
powered (4 sec otherwise)
D0
Reserved
R
0
Reserved. Do not write 1 to this location.
LAYOUT
The following layout suggestions should provide optimum performance from the TSC2100. However, many portable
applications have conflicting requirements concerning power, cost, size, and weight. In general, most portable devices
have fairly clean power and grounds because most of the internal components are very low power. This situation means
less bypassing for the converter power and less concern regarding grounding. Still, each situation is unique and the
following suggestions should be reviewed carefully.
For optimum performance, care must be taken with the physical layout of the TSC2100 circuitry. The basic SAR architecture
is sensitive to glitches or sudden changes on the power supply, reference, ground connections, and digital inputs that occur
just prior to latching the output of the analog comparator. Therefore, during any single conversion for an n-bit SAR converter,
there are n windows in which large external transient voltages can easily affect the conversion result. Such glitches might
originate from switching power supplies, nearby digital logic, and high power devices. The degree of error in the digital
output depends on the reference voltage, layout, and the exact timing of the external event. The error can change if the
external event changes in time with respect to the timing of the critical n windows.
With this in mind, power to the TSC2100 must be clean and well bypassed. A 0.1-F ceramic bypass capacitor must be
placed as close to the device as possible. A 1-F to 10-F capacitor may also be needed if the impedance between the
TSC2100 supply pins and the system power supply is high.
A bypass capacitor on the VREF pin is generally not needed because the reference is buffered by an internal op-amp,
although it can be useful to reduce reference noise level. If an external reference voltage originates from an op-amp, make
sure that it can drive any bypass capacitor that is used without oscillation.