參數(shù)資料
型號(hào): TSC21020F-20MASB
英文描述: IC CYCLONE III FPGA 16K 484FBGA
中文描述: 數(shù)字信號(hào)處理器| 32位|的CMOS | RAD數(shù)據(jù)通信硬|美巡賽| 223PIN |陶瓷
文件頁數(shù): 35/51頁
文件大?。?/td> 763K
代理商: TSC21020F-20MASB
35
TSC21020F
4153F
AERO
06/03
External Memory Three-State Control
Figure 9.
External Memory Three-State Control
Parameter
20 MHz
Frequency
Dependency
(1)
Unit
Min
Max
Min
Max
t
STS
XTS, Setup before CLKIN
High
14
50
14 + DT/4
t
CK
ns
t
DADTS
XTS Delay after
Address, Select
28
28 + 7DT/8
ns
t
DSTS
XTS, Delay after XRD,
XWR Low
16
16 + DT/2
ns
t
DTSD
Memory Interface
Disable before CLKIN High
0
DT/4
ns
t
DTSAE
XTS High to Address,
Select Enable
0
ns
Notes:
1. DT = t
CK
- 50 ns
XTS should only be asserted (low) during an active memory access cycle.
Memory Interface = PMA23-0, PMD47-0, PMS1-0, PMRD, PMWR, PMPAGE,
DMA31-0, DMD39-0, DMS3-0, DMRD, DMWR, DMPAGE.
Address = PMA23-0, DMA31-0, Select = PMS1-0, DMS3-0
x = PM or DM.
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