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參數(shù)資料
| 型號： | TSC21020F-20MASB |
| 英文描述： | IC CYCLONE III FPGA 16K 484FBGA |
| 中文描述： | 數(shù)字信號處理器| 32位|的CMOS | RAD數(shù)據(jù)通信硬|美巡賽| 223PIN |陶瓷 |
| 文件頁數(shù)： | 44/51頁 |
| 文件大小： | 763K |
| 代理商： | TSC21020F-20MASB |
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44
TSC21020F
4153F
–
AERO
–
06/03
where PD is power dissipation and
θ
CA
is the case-to-ambient thermal resistance. The
value of PD depends on your application; the method for calculating PD is shown under
"Power Dissipation" below.
θ
CA
varies with airflow. Table 9 shows a range of
θ
CA
values.
The TSC21020F is also available in a 256-pin MQFPF package (Ceramic). The pack-
age uses a cavity-up configuration.
Table 11.
Maximum
θ
CA
for Various Airflow Values
Airflow (m/s)
0
Power Dissipation
Total power dissipation has two components: one due to internal circuitry and one due
to the switching of external output drivers. Internal power dissipation is dependent on
the instruction execution sequence and the data values involved. Internal power dissipa-
tion is calculated in the following way:
P
INT =
I
DDIN
x V
DD
The external component of total power dissipation is caused by the switching of output
pins. Its magnitude depends on:
1) the number of output pins that switch during each cycle(O),
2) the maximum frequency at which they can switch (f),
3) their load capacitance (C), and
4) their voltage swing (V
DD
).
It is calculated by:
P
EXT =
O x C x V
DD
The load capacitance should include the processor
’
s package capacitance (C
IN
). The
switching frequency includes driving the load high and then back low. Address and data
pins can drive high and low at a maximum rate of 1/(2t
CK
). The write strobes can switch
every cycle at a frequency of 1/tCK. Select pins switch at 1/(2t
CK
), but 2 DM and 2 PM
selects can switch on each cycle. If only one bank is accessed, no select line will switch.
2
x f
Example:
Estimate P
EXT
with the following assumptions:
A system with one RAM bank each of PM (48 bits) and DM (32 bits).
32 K x 8 RAM chips are used, each with a load of 10 pF.
Single-precision mode is enabled so that only 32 data pins can switch at once.
PM and DM writes occur every other cycle, with 50% of the pins switching.
The instruction cycle rate is 20 MHz (t
CK
= 50 ns) and V
DD
= 5.0V.
0.5
1
1.5
MQFPF
31.5
°
C/W
25
°
C/W
21.5
°
C/W
19
°
C/W
CPGA
14.5
°
C/W
11.2
°
C/W
8.8
°
C/W
7.8
°
C/W
Note:
θ
JC
is 1
°
C/W for CPGA.
θ
JC
is 0.3
°
C/W for MQFPF.
Maximum recommended T
J
is 130
°
C.
As per method 1012 MIL-STD-883. Ambient temperature: 25
°
C. Power: 3.5W.
相關(guān)PDF資料 |
PDF描述 |
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| TSC21020F-20MASC | IC CYCLONE III FPGA 16K 164 MBGA |
| TSC21020F-20MASL1 | IC CYCLONE III FPGA 16K 240PQFP |
| TSC21020F-20MASL2 | IC CYCLONE III FPGA 16K 256 UBGA |
| TSC21020F-20MASL3 | IC CYCLONE III FPGA 16K 256UBGA |
| TSC21020F-20MB | FPGA, CYCLONE III, 16K LE, 256UBGA Programmable Logic Type:FPGA; Logic IC function:FPGA; Logic IC family:Cyclone III; Logic IC Base Number:3; I/O lines, No. of:168; |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| TSC21020F-20MASC | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:DSP|32-BIT|CMOS| RAD HARD|PGA|223PIN|CERAMIC |
| TSC21020F-20MASL1 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:DSP|32-BIT|CMOS| RAD HARD|PGA|223PIN|CERAMIC |
| TSC21020F-20MASL2 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:DSP|32-BIT|CMOS| RAD HARD|PGA|223PIN|CERAMIC |
| TSC21020F-20MASL3 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:DSP|32-BIT|CMOS| RAD HARD|PGA|223PIN|CERAMIC |
| TSC21020F-20MB | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:DSP|32-BIT|CMOS| RAD HARD|QFL|256PIN|CERAMIC |
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