參數(shù)資料
型號: TSC21020F-20MASL3
英文描述: IC CYCLONE III FPGA 16K 256UBGA
中文描述: 數(shù)字信號處理器| 32位|的CMOS | RAD數(shù)據(jù)通信硬|美巡賽| 223PIN |陶瓷
文件頁數(shù): 31/51頁
文件大小: 763K
代理商: TSC21020F-20MASL3
31
TSC21020F
4153F
AERO
06/03
Clock Signal
Figure 3.
Clock
Reset
Parameter
20 MHz
Unit
Min
Max
T
CK
CLKIN Period
50
150
ns
t
CKH
CLKIN Width High
10
ns
t
CKL
CLKIN Width Low
10
ns
Parameter
20 MHz
Frequency
Dependency
(1)
Unit
Min
Max
Min
Max
t
WRST
(2)
RESET Width Low
200
4t
CK
ns
t
SRST
before CLKIN High
(3)
RESET Setup
29
50
29 + DT/2
30
ns
Notes:
1. DT = t
CK
- 50 ns
2. Applies after the power-up sequence is complete. At power up, the Internal Phase
Locked Loop requires no more than 1000CLKIN cycles while RESET is low, assum-
ing stable V
DD
and CLKIN (not including clock oscillator start-up time).
3. Specification only applies in cases where multiple TSC21020F processors are
required to execute in program counter lock-step (all processors start execution at
location 8 in the same cycle). See the Hardware Configuration chapter of the
ADSP-21020 User’s Manual from Analog Devices
for reset sequence information.
相關(guān)PDF資料
PDF描述
TSC21020F-20MB FPGA, CYCLONE III, 16K LE, 256UBGA Programmable Logic Type:FPGA; Logic IC function:FPGA; Logic IC family:Cyclone III; Logic IC Base Number:3; I/O lines, No. of:168;
TSC21020F-20MB-E IC CYCLONE III FPGA 16K 484UBGA
TSC21020F-20MBP833 IC CYCLONE III FPGA 25K 144-EQFP
TSC21020F-20MBSB IC CYCLONE III FPGA 25K 144 EQFP
TSC21020F-20MBSC IC CYCLONE III FPGA 25K 256 FBGA
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
TSC21020F-20MB 制造商:未知廠家 制造商全稱:未知廠家 功能描述:DSP|32-BIT|CMOS| RAD HARD|QFL|256PIN|CERAMIC
TSC21020F-20MB/883 制造商:未知廠家 制造商全稱:未知廠家 功能描述:DSP|32-BIT|CMOS| RAD HARD|QFL|256PIN|CERAMIC
TSC21020F-20MB-E 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:Rad. Hard 32/40-bit IEEE Floating Point DSP
TSC21020F-20MBP833 制造商:未知廠家 制造商全稱:未知廠家 功能描述:DSP|32-BIT|CMOS| RAD HARD|QFL|256PIN|CERAMIC
TSC21020F-20MBSB 制造商:未知廠家 制造商全稱:未知廠家 功能描述:DSP|32-BIT|CMOS| RAD HARD|QFL|256PIN|CERAMIC