- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄365969 > TSC21020F-20MB FPGA, CYCLONE III, 16K LE, 256UBGA Programmable Logic Type:FPGA; Logic IC function:FPGA; Logic IC family:Cyclone III; Logic IC Base Number:3; I/O lines, No. of:168; PDF資料下載
參數(shù)資料
| 型號(hào)： | TSC21020F-20MB |
| 英文描述： | FPGA, CYCLONE III, 16K LE, 256UBGA Programmable Logic Type:FPGA; Logic IC function:FPGA; Logic IC family:Cyclone III; Logic IC Base Number:3; I/O lines, No. of:168; |
| 中文描述： | 數(shù)字信號(hào)處理器| 32位|的CMOS | RAD數(shù)據(jù)通信硬| QFL | 256PIN |陶瓷 |
| 文件頁數(shù)： | 6/51頁 |
| 文件大?。?/td> | 763K |
| 代理商： | TSC21020F-20MB |
第1頁第2頁第3頁第4頁第5頁當(dāng)前第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁
6
TSC21020F
4153F
–
AERO
–
06/03
Architecture
Overview
Figure 1 shows a block diagram of the TSC21020F. The processor features:
Three Computation Units (ALU, Multiplier, and Shifter) with a Shared Data Register
File
Two Data Address Generators (DAG 1, DAG 2)
Program Sequencer with Instruction Cache
32-bit Timer
Memory Buses and Interface
JTAG Test Access Port and On-chip Emulation Support
Computation Units
The TSC21020F contains three independent computation units: an ALU, a multiplier
with fixed-point accumulator, and a shifter. In order to meet a wide variety of processing
needs, the computation units process data in three formats: 32-bit fixed-point, 32-bit
floating-point and 40-bit floating-point. The floating-point operations are single-precision
IEEE-compatible (IEEE Standard 754/854). The 32-bit floating-point format is the stan-
dard IEEE format, whereas the 40-bit IEEE extended- precision format has eight
additional LSBs of mantissa for greater accuracy.
The multiplier performs floating-point and fixed-point multiplication as well as fixed-point
multiply/add and multiply/subtract operations. Integer products are 64 bits wide, and the
accumulator is 80 bits wide. The ALU performs 45 standard arithmetic and logic opera-
tions, supporting both fixed-point and floating-point formats. The shifter performs 19
different operations on 32-bit operands. These operations include logical and arithmetic
shifts, bit manipulation, field deposit, and extract and derive exponent operations.
The computation units perform single-cycle operations; there is no computation pipeline.
The three units are connected in parallel rather than serially, via multiple-bus connec-
tions with the 10-port data register file. The output of any computation unit may be used
as the input of any unit on the next cycle. In a multifunction computation, the ALU and
multiplier perform independent, simultaneous operations.
Data Register File
The TSC21020F's general-purpose data register file is used for transferring data
between the computation units and the data buses, and for storing intermediate results.
The register file has two sets (primary and alternate) of sixteen 40-bit registers each, for
fast context switching.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| TSC21020F-20MB-E | IC CYCLONE III FPGA 16K 484UBGA |
| TSC21020F-20MBP833 | IC CYCLONE III FPGA 25K 144-EQFP |
| TSC21020F-20MBSB | IC CYCLONE III FPGA 25K 144 EQFP |
| TSC21020F-20MBSC | IC CYCLONE III FPGA 25K 256 FBGA |
| TSC21020F-20MBSL1 | IC CYCLONE III FPGA 25K 324 FBGA |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| TSC21020F-20MB/883 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:DSP|32-BIT|CMOS| RAD HARD|QFL|256PIN|CERAMIC |
| TSC21020F-20MB-E | 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:Rad. Hard 32/40-bit IEEE Floating Point DSP |
| TSC21020F-20MBP833 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:DSP|32-BIT|CMOS| RAD HARD|QFL|256PIN|CERAMIC |
| TSC21020F-20MBSB | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:DSP|32-BIT|CMOS| RAD HARD|QFL|256PIN|CERAMIC |
| TSC21020F-20MBSC | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:DSP|32-BIT|CMOS| RAD HARD|QFL|256PIN|CERAMIC |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。