參數(shù)資料
型號: TSC21020F-20MBSC
英文描述: IC CYCLONE III FPGA 25K 256 FBGA
中文描述: 數(shù)字信號處理器| 32位|的CMOS | RAD數(shù)據(jù)通信硬| QFL | 256PIN |陶瓷
文件頁數(shù): 27/51頁
文件大小: 763K
代理商: TSC21020F-20MBSC
27
TSC21020F
4153F
AERO
06/03
Table 9.
Multifunction Compute Operations
Floating-Point
Fm = F3-0
(1)
F7-4, Fa = F11-8 + F15-12
Fm = F3-0
(1)
F7-4, Fa = F11-8 - F15-12
Fm = F3-0
(1)
F7-4, Fa = FLOAT R11-8 by R15-12
Fm = F3-0
(1)
F7-4, Fa = FIX R11-8 by R15-12
Fm = F3-0
(1)
F7-4, Fa = (F11-8 + F15-12)/2
Fm = F3-0
(1)
F7-4, Fa = ABS F11-8
Fm = F3-0
(1)
F7-4, Fa = MAX (F11-8, F15-12)
Fm = F3-0
(1)
F7-4, Fa = MIN (F11-8 + F15-12)
Fm = F3-0
(1)
F7-4, Fa = F11-8 + F15-12,
Fs = F11-8 - F15-12
Ra, Rm Any register file location (fixed-point)
R3-0 R3, R2, R1, R0
R7-4 R7, R6, R5, R4
R11-8 R11, R10, R9, R8
R15-12 R15, R14, R13, 12
Fa, Fm Any register file location (floating-point)
F3-0 F3, F2, F1, F0
F7-4 F7, F6, F5, F4
F11-8 F11, F10, F9, F8
F15-12 F15, F14, F13, F12
(SSF) X-input signed, Y-input signed, fractional inputs
(SSFR) X-input signed, Y-input signed, fractional inputs, rounded output
Table 10.
Interrupt Vector Addresses and Priorities
No
Vector Address (Hex) Function
0
0x00
Reserved
1
(1)
0x08
Reset
2
0x10
Reserved
3
0x18
Status stack or loop stack overflow or PC stack full
4
0x20
Timer = 0 (high priority option)
5
0x28
IRQ3 asserted
6
0x30
IRQ2 asserted
7
0x38
IRQ1 asserted
8
0x40
IRQ0 asserted
9
0x48
Reserved
10
0x50
Reserved
11
0x58
DAG 1 circular buffer 7 overflow
12
0x60
DAG 2 circular buffer 15 overflow
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