參數(shù)資料
型號(hào)： TSC21020F-20MBSL2
英文描述： IC CYCLONE III FPGA 25K 324-FBGA
中文描述： 數(shù)字信號(hào)處理器| 32位|的CMOS | RAD數(shù)據(jù)通信硬| QFL | 256PIN |陶瓷
文件頁(yè)數(shù)： 41/51頁(yè)
文件大?。?/td> 763K
代理商： TSC21020F-20MBSL2
41
TSC21020F
4153F
–
AERO
–
06/03
Figure 14.
Equivalent Device Loading for AC Measurements (Includes all Fixtures)
Example System Hold
Time Calculation
To determine the data output hold time in a particular system, first calculate t
DECAY
using
the above equation. Choose
V to be the difference between the TSC21020F
’
s output
voltage and the input threshold for the device requiring the hold time. A typical
V will be
0.4V. C
L
is the total bus capacitance (per data line), and I
L
is the total leakage or three-
state current (per data line). The hold time will be t
DECAY
plus the minimum disable time
(i.e. t
HDWD
for the write cycle).
Figure 15.
Voltage Reference Levels for AC Measurements (Except Output
Enable/Disable)
Capacitive Loading
Output delays are based on standard capacitive loads: 100 pF on address, select, page
and strobe pins, and 50 pF on all others (see Figure 14). For different loads, these tim-
ing parameters should be derated. See the Hardware Configuration chapter of the
ADSP-21020 User
’
s Manual from Analog Devices for further information on derating of
timing specifications.
Figures 16 and 17 show how the output rise time varies with capacitance. Figures 18
and 19 show how output delays vary with capacitance. Note that the graphs may not be
linear outside the ranges shown.
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
TSC21020F-20MBSL3 制造商:未知廠家 制造商全稱:未知廠家 功能描述:DSP|32-BIT|CMOS| RAD HARD|QFL|256PIN|CERAMIC
TSC21020F-20MC-E 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:Rad. Hard 32/40-bit IEEE Floating Point DSP
TSC21020F-20MC-SV 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:Rad. Hard 32/40-bit IEEE Floating Point DSP
TSC21020F-20SA 制造商:未知廠家 制造商全稱:未知廠家 功能描述:DSP|32-BIT|CMOS| RAD HARD|PGA|223PIN|CERAMIC
TSC21020F-20SA/883 制造商:未知廠家 制造商全稱:未知廠家 功能描述:DSP|32-BIT|CMOS| RAD HARD|PGA|223PIN|CERAMIC
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