參數(shù)資料
型號: TSC80251G2D-24CB
廠商: TEMIC SEMICONDUCTORS
元件分類: 8位微控制器
英文描述: 8/16-bit Microcontroller with Serial Communication Interfaces
中文描述: 16位產(chǎn)品微控制器的串行通信接口
文件頁數(shù): 22/63頁
文件大小: 878K
代理商: TSC80251G2D-24CB
Rev. A - May 7, 1999
22
TSC80251G2D
Table 26. Summary of Move Instructions (1/3)
Notes:
1. A shaded cell denotes an instruction in the C51 Architecture.
2. Extended memory addressed is in the region specified by DPXL (reset value= 01h).
3. If this instruction addresses external memory location, add N+1 to the number of states (N: number of wait states).
4. If this instruction addresses external memory location, add N+2 to the number of states (N: number of wait states).
Table 27. Summary of Move Instructions (2/3)
Notes:
1. Instructions that move bits are in Table 29.
2. Move instructions from the C51 Architecture.
3. If this instruction addresses an I/O Port (Px, x= 0-3), add 1 to the number of states. Add 2 if it addresses a Peripheral SFR.
4. Apply note 3 for each dir8 operand.
Move to High word
Move with Sign extension
Move with Zero extension
Move Code
Move eXtended
MOVH <dest>, <src>
MOVS <dest>, <src>
MOVZ <dest>, <src>
MOVC A, <src>
MOVX <dest>, <src>
dest opnd
31:16
src opnd
dest opnd
src opnd with sign extend
dest opnd
src opnd with zero extend
(A)
src opnd
dest opnd
src opnd
Mnemonic
<dest>, <src>
(2)
Comments
Binary Mode
Source Mode
Bytes
States
Bytes
States
MOVH
DRk, #data16
16-bit immediate data into upper word of dword register
5
3
4
2
MOVS
WRj, Rm
Byte register to word register with sign extension
3
2
2
1
MOVZ
WRj, Rm
Byte register to word register with zeros extension
3
2
2
1
MOVC
A, @A +DPTR
Code byte relative to DPTR to ACC
1
6
(3)
6
(3)
1
6
(3)
6
(3)
A, @A +PC
Code byte relative to PC to ACC
Extended memory (8-bit address) to ACC
(2)
Extended memory (16-bit address) to ACC
(2)
ACC to extended memory (8-bit address)
(2)
ACC to extended memory (16-bit address)
(2)
1
1
MOVX
A, @Ri
1
4
1
5
A, @DPTR
1
3
(4)
1
3
(4)
@Ri, A
1
4
1
4
@DPTR, A
1
4
(3)
1
4
(3)
Move
(1)
MOV <dest>, <src>
dest opnd
src opnd
Mnemonic
<dest>, <src>
(2)
Comments
Binary Mode
Source Mode
Bytes
States
Bytes
States
MOV
A, Rn
Register to ACC
1
1
2
2
A, dir8
Direct address (on-chip RAM or SFR) to ACC
2
1
(3)
2
1
(3)
A, @Ri
Indirect address to ACC
1
2
2
3
A, #data
Immediate data to ACC
2
1
2
1
Rn, A
ACC to register
1
1
2
2
Rn, dir8
Direct address (on-chip RAM or SFR) to register
2
1
(3)
3
2
(3)
Rn, #data
Immediate data to register
2
1
3
2
dir8, A
ACC to direct address (on-chip RAM or SFR)
2
2
(3)
2
(3)
3
(4)
3
(3)
3
(3)
2
2
(3)
3
(3)
3
(4)
4
(3)
3
(3)
dir8, Rn
Register to direct address (on-chip RAM or SFR)
2
3
dir8, dir8
Direct address to direct address (on-chip RAM or SFR)
3
3
dir8, @Ri
Indirect address to direct address (on-chip RAM or SFR)
2
3
dir8, #data
Immediate data to direct address (on-chip RAM or SFR)
3
3
@Ri, A
ACC to indirect address
1
3
2
4
@Ri, dir8
Direct address (on-chip RAM or SFR) to indirect address
2
3
(3)
3
4
(3)
@Ri, #data
Immediate data to indirect address
2
3
3
4
DPTR, #data16
Load Data Pointer with a 16-bit constant
3
2
3
2
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