參數(shù)資料
型號： TSL2562CS
廠商： TAOS Inc.
英文描述： LOW-VOLTAGE LIGHT-TO-DIGITAL CONVERTER
中文描述： 低壓光到數(shù)字轉(zhuǎn)換器
文件頁數(shù)： 12/38頁
文件大小： 443K
代理商： TSL2562CS
TSL2562, TSL2563
LOW-VOLTAGE
LIGHT-TO-DIGITAL CONVERTER
TAOS066J
MAY 2007
12
Copyright 2007, TAOS Inc.
The
LUMENOLOGY
Company
www.taosinc.com
Wr
8
Data Byte 1
Slave Address
S
1
A
A
8
1
1
1
Command Code
P
Data Byte N
A
8
1
1
Byte Count = N
A
A
...
7
8
1
1
Data Byte 2
A
8
1
...
Figure 14. SMBus Block Write or I
2
C Write Protocols
NOTE: The I
2
C write protocol does not use the Byte Count packet, and the Master will continue sending Data Bytes until the Master initiates a
Stop condition. See the Command Register on page 13 for additional information regarding the Block Read/Write protocol.
Wr
7
Byte Count = N
Slave Address
S
1
A
A
8
1
1
1
Command Code
P
Data Byte N
A
8
1
1
Slave Address
A
A
...
7
8
1
1
Data Byte 2
A
8
1
...
Data Byte 1
A
8
1
1
Sr
1
Rd
1
Figure 15. SMBus Block Read or I
2
C Read (Combined Format) Protocols
NOTE: The I
2
C read protocol does not use the Byte Count packet, and the Master will continue receiving Data Bytes until the Master initiates
a Stop Condition. See the Command Register on page 13 for additional information regarding the Block Read/Write protocol.
Register Set
The TSL256x is controlled and monitored by sixteen registers (three are reserved) and a command register
accessed through the serial interface. These registers provide for a variety of control functions and can be read
to determine results of the ADC conversions. The register set is summarized in Table 2.
Table 2. Register Address
ADDRESS
0h
1h
2h
3h
4h
5h
6h
7h
8h
9h
Ah
Bh
Ch
Dh
Eh
Fh
RESISTER NAME
COMMAND
CONTROL
TIMING
THRESHLOWLOW
THRESHLOWHIGH
THRESHHIGHLOW
THRESHHIGHHIGH
INTERRUPT
CRC
ID
DATA0LOW
DATA0HIGH
DATA1LOW
DATA1HIGH
REGISTER FUNCTION
Specifies register address
Control of basic functions
Integration time/gain control
Low byte of low interrupt threshold
High byte of low interrupt threshold
Low byte of high interrupt threshold
High byte of high interrupt threshold
Interrupt control
Reserved
Factory test — not a user register
Reserved
Part number/ Rev ID
Reserved
Low byte of ADC channel 0
High byte of ADC channel 0
Low byte of ADC channel 1
High byte of ADC channel 1
The mechanics of accessing a specific register depends on the specific SMB protocol used. Refer to the section
on SMBus protocols. In general, the COMMAND register is written first to specify the specific control/status
register for following read/write operations.
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