參數(shù)資料
型號(hào)： TSL2562CS
廠商： TAOS Inc.
英文描述： LOW-VOLTAGE LIGHT-TO-DIGITAL CONVERTER
中文描述： 低壓光到數(shù)字轉(zhuǎn)換器
文件頁(yè)數(shù)： 9/38頁(yè)
文件大小： 443K
代理商： TSL2562CS
TSL2562, TSL2563
LOW-VOLTAGE
LIGHT-TO-DIGITAL CONVERTER
TAOS066J
MAY 2007
9
The
LUMENOLOGY
Company
Copyright 2007, TAOS Inc.
www.taosinc.com
PRINCIPLES OF OPERATION
Analog-to-Digital Converter
The TSL256x contains two integrating analog-to-digital converters (ADC) that integrate the currents from the
channel 0 and channel 1 photodiodes. Integration of both channels occurs simultaneously, and upon completion
of the conversion cycle the conversion result is transferred to the channel 0 and channel 1 data registers,
respectively. The transfers are double buffered to ensure that invalid data is not read during the transfer. After
the transfer, the device automatically begins the next integration cycle.
Digital Interface
Interface and control of the TSL256x is accomplished through a two-wire serial interface to a set of registers
that provide access to device control functions and output data. The serial interface is compatible with System
Management Bus (SMBus) versions 1.1 and 2.0, and I
2
C bus Fast-Mode. The TSL256x offers three slave
addresses that are selectable via an external pin (ADDR SEL). The slave address options are shown in Table 1.
Table 1. Slave Address Selection
ADDR SEL TERMINAL LEVEL
GND
Float
VDD
SLAVE ADDRESS
0101001
0111001
1001001
SMB ALERT ADDRESS
0001100
0001100
0001100
NOTE: The Slave and SMB Alert Addresses are 7 bits. Please note the SMBus and I
2
C protocols on pages 9 through 12. A read/write bit should
be appended to the slave address by the master device to properly communicate with the TSL256X device.
SMBus and I
2
C Protocols
Each
Send
and
Write
protocol is, essentially, a series of bytes. A byte sent to the TSL256x with the most
significant bit (MSB) equal to 1 will be interpreted as a COMMAND byte. The lower four bits of the COMMAND
byte form the register select address (see Table 2), which is used to select the destination for the subsequent
byte(s) received. The TSL256x responds to any Receive Byte requests with the contents of the register
specified by the stored register select address.
The TSL256X implements the following protocols of the SMB 2.0 specification:
Send Byte Protocol
Receive Byte Protocol
Write Byte Protocol
Write Word Protocol
Read Word Protocol
Block Write Protocol
Block Read Protocol
The TSL256X implements the following protocols of the Philips Semiconductor I
2
C specification:
I
2
C Write Protocol
I
2
C Read (Combined Format) Protocol
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