參數(shù)資料
型號(hào)： TSPC106AVGSU66CG
英文描述： MEMORY CONTROLLER
中文描述： 內(nèi)存控制器
文件頁(yè)數(shù)： 2/40頁(yè)
文件大小： 569K
代理商： TSPC106AVGSU66CG
2
TSPC106
2102B
–
HIREL
–
02/02
Figure 1.
TSPC106 Block Diagram
Functional
Description
The TSPC106 provides a PowerPC
microprocessor CHRP-compliant bridge between
the PowerPC microprocessor family and the PCI bus. CHRP is a set of specifications
that defines a unified personal computer architecture and brings the combined advan-
tages of the Power Macintosh
platform and the standard PC environment to both
system vendors and users. PCI support allows system designers to rapidly design sys-
tems using peripherals already designed for PCI and other standard interfaces available
in the personal computer hardware environment. These open specifications make it
easier for system vendors to design computers capable of running multiple operating
systems. The TSPC106 integrates secondary cache control and a high-performance
memory controller. The TSPC106 uses an advanced 3.3V CMOS process technology
and is fully compatible with TTL devices.
The TSPC106 supports a programmable interface to a variety of PowerPC microproces-
sors operating at select bus speeds. The 60x address bus is 32 bits wide; the data bus
is 64 bits wide. The 60x processor interface of the TSPC106 uses a subset of the 60x
bus protocol, supporting single-beat and burst data transfers. The address and data
buses are decoupled to support pipelined transactions.
Memory
Interface
Power Management
60x Processor
Interface
L2 Cache
Interface
Error/Interrupt
Control
Target
Master
Configuration
Registers
PCI Interface
Memory
L2
60x Bus
PCI Bus
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