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參數(shù)資料
| 型號： | TSPC603RMGSU12LC |
| 元件分類： | 微處理器 |
| 英文描述： | MICROPROCESSOR|32-BIT|CMOS|BGA|255PIN|CERAMIC |
| 中文描述： | 微處理器| 32位|的CMOS | BGA封裝| 255PIN |陶瓷 |
| 文件頁數(shù)： | 17/42頁 |
| 文件大?。?/td> | 961K |
| 代理商： | TSPC603RMGSU12LC |
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17
TSPC603R
2125A–12/01
Dynamic
Characteristics
Clock AC Specifications
Table 10 provides the clock AC timing specifications as defined in Figure 5.
Notes:
1. Rise and fall times for the SYSCLK input are measured from 0.4V to 2.4V.
2. Cycle-to-cycle jitter is guaranteed by design.
3. Timing is guaranteed by design and characterization, and is not tested.
4. PLL relock time is the maximum amount of time required for PLL lock after a stable V
dd
, OV
dd
, AV
dd
and SYSCLK are
reached during the power-on reset sequence. This specification also applies when the PLL has been disabled and subse-
quently re-enabled during sleep mode. Also note that HRESET must be held asserted for a minimum of 255 bus clocks after
the PLL relock time (100 μs) during the power-on reset sequence.
5.
Caution
: The SYSCLK frequency and PLL_CFG[0-3] settings must be chosen such that the resulting SYSCLK (bus) fre-
quency, CPU (core) frequency, and PLL (VCO) frequency do not exceed their respective maximum or minimum operating
frequencies. Refer to the PLL_CFG[0-3] signal description for valid PLL_CFG[0-3] settings.
Figure 5.
SYSCLK Input Timing Diagram
Input AC specifications
Table 10.
Clock AC Timing Specifications
V
dd
= A
V
dd
= 2.5V
±
5%; O
V
dd
= 3.3
±
5%V dc, GND = 0V dc, -55
°
C
≤
T
C
≤
125
°
C
Num
Characteristics
166 MHz
200 MHz
233 MHz
266 MHz
300 MHz
Unit
Note
Min
Max
Min
Max
Min
Max
Min
Max
Min
Max
Processor Frequency
150
166
150
200
180
233
180
266
180
300
MHz
5
VCO Frequency
300
332
300
400
360
466
360
532
360
600
MHz
5
SYSCLK (bus)
Frequency
25
66.7
33.3
66.7
33.3
75
33.3
75
33.3
75
MHz
5
1
SYSCLK Cycle Time
15
30
13.3
30
13.3
30
13.3
30
13.3
30
ns
2,3
SYSCLK Rise and Fall
Time
-
2.0
-
2.0
-
2.0
-
2.0
-
2.0
ns
1
4
SYSCLK Duty Cycle
(1.4V measured)
40.0
60.0
40.0
60.0
40.0
60.0
40.0
60.0
40.0
60.0
%
3
SYSCLK Jitter
-
±150
-
±150
-
±150
-
±150
-
±150
ps
2
603r Internal PLL
Relock Time
-
100
-
100
-
100
-
100
-
100
μs
3,4
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