參數(shù)資料
型號(hào)： TSPC603RVGS14LC
英文描述： MICROPROCESSOR|32-BIT|CMOS|BGA|255PIN|CERAMIC
中文描述： 微處理器| 32位|的CMOS | BGA封裝| 255PIN |陶瓷
文件頁(yè)數(shù)： 14/42頁(yè)
文件大?。?/td> 961K
代理商： TSPC603RVGS14LC
14
TSPC603R
2125A–12/01
Transition to full-power state takes no more than a few processor cycles.
PLL running and locked to SYSCLK.
NAP MODE:
The nap mode disables the 603r but still maintains the phase locked loop (PLL)
and the time base/decrementer. The time base can be used to restore the 603r to full-on state
after a programmed amount of time. Because bus snooping is disabled for nap and sleep
mode, a hardware handshake using the quiesce request (QREQ) and quiesce acknowledge
(QACK) signals are requires to maintain data coherency. The 603r will assert the QREQ signal
to indicate that it is ready to disable bus snooping. When the system has ensured that snoop-
ing is no longer necessary, it will assert QACK and the 603r will enter the sleep or nap mode.
Time base/decrementer still enabled.
Most functional units disabled (including bus snooping).
All nonessential input receivers disables.
Nap mode sequence:
- Set nap bit (HID0[9] = 1).
- 603r asserts quiesce request (QREQ) signal.
- System asserts quiesce acknowledge (QACK) signal.
- 603r enters sleep mode after several processor clocks.
Several methods of returning to full-power mode:
- Assert INT, SPI, MCP or decrementer interrupts.
- Assert hard reset or soft reset.
Transition to full-power takes no more than a few processor cycles.
PLL running and locked to SYSCLK.
SLEEP MODE:
Sleep mode consumes the least amount of power of the four modes since all
functional units are disabled. To conserve the maximum amount of power, the PLL may be
disabled and the SYSCLK may be removed. Due to the fully static design of the 603r, internal
processor state is preserved when no internal clock is present. Because the time base and
decrementer are disabled while the 603r is in sleep mode, the 603r’s time base contents will
have to be updated from an external time base following sleep mode if accurate time-of-day
maintenance is required. Before the 603r enters the sleep mode, the 603r will assert the
QREQ signal to indicate that it is ready to disable bus snooping. When the system has
ensured that snooping is no longer necessary, it will assert QACK and the 603r will enter the
sleep mode.
All functional units disabled (including bus snooping and time base).
All nonessential input receivers disabled:
- Internal clock regenerators disabled.
- PLL still running (see below).
Sleep mode sequence:
- Set sleep bit (HID0[10] = 1).
- 603r asserts quiesce request (QREQ).
- System asserts quiesce acknowledge (QACK).
- 603r enters sleep mode after several processor clocks.
Several methods of returning to full-power mode:
- Assert INT, SMI, or MCP interrupts.
- Assert hard reset or soft reset.
PLL may be disabled and SYSCLK may be removed while in sleep mode.
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參數(shù)描述
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