參數(shù)資料
型號: TSPC603RVGSB/Q14LC
廠商: ATMEL CORP
元件分類: 微控制器/微處理器
英文描述: 32-BIT, 300 MHz, RISC PROCESSOR, CBGA255
封裝: 21 X 21 MM, 3.84 MM HEIGHT, 1.27 MM PITCH, CERAMIC, CI-CGA-255
文件頁數(shù): 10/132頁
文件大?。?/td> 10886K
代理商: TSPC603RVGSB/Q14LC
18
7593L–AVR–09/12
AT90USB64/128
Note that the Status Register is not automatically stored when entering an interrupt routine, nor
restored when returning from an interrupt routine. This must be handled by software.
When using the CLI instruction to disable interrupts, the interrupts will be immediately disabled.
No interrupt will be executed after the CLI instruction, even if it occurs simultaneously with the
CLI instruction. The following example shows how this can be used to avoid interrupts during the
timed EEPROM write sequence.
When using the SEI instruction to enable interrupts, the instruction following SEI will be exe-
cuted before any pending interrupts, as shown in this example.
Assembly code example
in
r16, SREG
; store SREG value
cli
; disable interrupts during timed sequence
sbi
EECR, EEMPE
; start EEPROM write
sbi
EECR, EEPE
out
SREG, r16
; restore SREG value (I-bit)
C code example
char
cSREG;
cSREG = SREG; /* store SREG value */
/* disable interrupts during timed sequence */
__disable_interrupt();
EECR |= (1<<EEMPE); /* start EEPROM write */
EECR |= (1<<EEPE);
SREG = cSREG; /* restore SREG value (I-bit) */
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