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參數(shù)資料
| 型號： | TSPC603RVGSB/Q14LC |
| 廠商： | ATMEL CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 32-BIT, 300 MHz, RISC PROCESSOR, CBGA255 |
| 封裝： | 21 X 21 MM, 3.84 MM HEIGHT, 1.27 MM PITCH, CERAMIC, CI-CGA-255 |
| 文件頁數(shù)： | 39/132頁 |
| 文件大?。?/td> | 10886K |
| 代理商： | TSPC603RVGSB/Q14LC |
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206
ATmega8535(L)
2502K–AVR–10/06
Analog-to-Digital
Converter
Features
10-bit Resolution
0.5 LSB Integral Non-linearity
±2 LSB Absolute Accuracy
65 - 260 s Conversion Time
Up to 15 kSPS at Maximum Resolution
8 Multiplexed Single Ended Input Channels
7 Differential Input Channels
2 Differential Input Channels with Optional Gain of 10x and 200x(1)
Optional Left Adjustment for ADC Result Readout
0 - V
CC ADC Input Voltage Range
Selectable 2.56V ADC Reference Voltage
Free Running or Single Conversion Mode
ADC Start Conversion by Auto Triggering on Interrupt Sources
Interrupt on ADC Conversion Complete
Sleep Mode Noise Canceler
Note:
1. The differential input channel are not tested for devices in PDIP and PLCC Package.
This feature is only guaranteed to work for devices in TQFP and QFN/MLF Packages.
The ATmega8535 features a 10-bit successive approximation ADC. The ADC is con-
nected to an 8-channel Analog Multiplexer which allows eight single-ended voltage
inputs constructed from the pins of Port A. The single-ended voltage inputs refer to 0V
(GND).
The device also supports 16 differential voltage input combinations. Two of the differen-
tial inputs (ADC1, ADC0 and ADC3, ADC2) are equipped with a programmable gain
stage, providing amplification steps of 0 dB (1x), 20 dB (10x), or 46 dB (200x) on the dif-
ferential input voltage before the A/D conversion. Seven differential analog input
channels share a common negative terminal (ADC1), while any other ADC input can be
selected as the positive input terminal. If 1x or 10x gain is used, 8-bit resolution can be
expected. If 200x gain is used, 7-bit resolution can be expected.
The ADC contains a Sample and Hold circuit which ensures that the input voltage to the
ADC is held at a constant level during conversion. A block diagram of the ADC is shown
in Figure 98.
The ADC has a separate analog supply voltage pin, AVCC. AVCC must not differ more
than ±0.3V from V
CC. See the paragraph “ADC Noise Canceler” on page 214 on how to
connect this pin.
Internal reference voltages of nominally 2.56V or AVCC are provided On-chip. The volt-
age reference may be externally decoupled at the AREF pin by a capacitor for better
noise performance.
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