參數(shù)資料
型號(hào): TSPC603RVGSU14LC
元件分類: 微處理器
英文描述: MICROPROCESSOR|32-BIT|CMOS|BGA|255PIN|CERAMIC
中文描述: 微處理器| 32位|的CMOS | BGA封裝| 255PIN |陶瓷
文件頁(yè)數(shù): 20/42頁(yè)
文件大?。?/td> 961K
代理商: TSPC603RVGSU14LC
20
TSPC603R
2125A–12/01
5. t
sysclk
is the period of the external bus clock (SYSCLK) in nanoseconds (ns). The numbers given in the table must be multi-
plied by the period of SYSCLK to compute the actual time duration (in nanoseconds) of the parameter in question.
6. Output signal transitions from GND to 2.0V or V
dd
to 0.8V.
7. Nominal precharge width for ABB and DBB is 0.5 * t
sysclk
.
8. Nominal precharge width for ARTRY is 1.0 * t
sysclk
.
Figure 8.
Output Timing Diagram
JTAG AC Timing
Specifications
Table 13.
JTAG AC Timing Specifications (independent of SYSCLK)
V
dd
= A
V
dd
= 2.5V
±
5%; O
V
dd
= 3.3
±
5%V dc, GND = 0V dc, C
L
= 50 pF, -55
°
C
T
C
125
°
C
Num
Characteristic
Min
Max
Unit
Notes
TCK frequency of operation
0
16
MHz
1
TCK cycle time
62.5
ns
2
TCK clock pulse width measured at 1.4V
25
ns
3
TCK rise and fall times
0
3
ns
4
TRST setup time to TCK rising edge
13
ns
1
5
TRST assert time
40
ns
6
Boundary scan input data setup time
6
ns
2
7
Boundary scan input data hold time
27
ns
2
8
TCK to output data valid
4
25
ns
3
9
TCK to output high impedance
3
24
ns
3
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