參數(shù)資料
型號(hào)： TSPC603RVGU10LC
元件分類(lèi)： 微處理器
英文描述： MICROPROCESSOR|32-BIT|CMOS|BGA|255PIN|CERAMIC
中文描述： 微處理器| 32位|的CMOS | BGA封裝| 255PIN |陶瓷
文件頁(yè)數(shù)： 33/42頁(yè)
文件大?。?/td> 961K
代理商： TSPC603RVGU10LC
33
TSPC603R
2125A–12/01
Alignment
00600
An alignment exception is caused when the 603e cannot perform a memory access for any
of the reasons described below:
The operand of a floating-point load or store instruction is not word-aligned.
The operand of lmw, stmw, lwarx, and stwcx, instructions are not aligned.
The operand of a single-register load or store operation is not aligned, and the 603e is in
little-endian mode.
The instruction is lmw, stmw, lswi, lwsx, stswi, stswx and the 603e is in little-endian mode.
The operand of dcbz is in storage that is write-through-required, or caching inhibited.
Program
00700
A program exception is caused by one of the following exception conditions, which
correspond to bit settings in SRR1 and arise during execution of an instruction:
Floating-point enabled exception—A floating-point enabled exception condition is
generated when the following condition is met: (MSR[FE0] | MSR[FE1]) & FPSCR[FEX] is
1. FPSCR[FEX] is set by the execution of a floating-point instruction that causes an
enabled exception or by the execution of one of the “move to FPSCR” instructions that
results in both an exception condition bit and its corresponding enable bit being set in the
FPSCR.
Illegal instruction—An illegal instruction program exception is generated when execution
of an instruction is attempted with an illegal opcode or illegal combination of opcode and
extended opcode fields (including PowerPC instructions not implemented in the 603e), or
when execution of an optional instruction not provided in the 603e is attempted (these do
not include those optional instructions that are treated as no-ops).
Privileged instruction—A privileged instruction type program exception is generated when
the execution of a privileged instruction is attempted and the MSR register user privilege
bit, MSR[PR], is set. In the 603e, this exception is generated for mtspr or mfspr with an
invalid SPR field if SPR[0] = 1 and MSR[PR] = 1. This may not be true for all PowerPC
processors.
Trap—A trap type program exception is generated when any of the conditions specified in
a trap instruction is met.
Floating-point
unavailable
00800
A floating-point unavailable exception is caused by an attempt to execute a floating-point
instruction (including floating-point load, store, and more instructions) when the floating-
point available bit is disabled, (MSR[FP] = 0).
Decrementer
00900
The decrementer exception occurs when the most significant bit of the decrementer (DEC)
register transitions from 0 to 1. Must also be enabled with the MSR[EE] bit.
Reserved
00A00–00BFF
—
System call
00C00
A system call exception occurs when a System Call (sc) instruction is executed.
Trace
00D00
A trace execution is taken when MSR[SE] = 1 or when the currently completing instruction
is a branch and MSR[BE] = 1.
Reserved
00E00
The 603e does not generate an exception to this vector. Other PowerPC processors may
use this vector for floating-point assist exceptions.
Reserved
00E10–00FFF
—
Instruction
translation miss
01000
An instruction translation miss exception is caused when an effective address for an
instruction fetch cannot be translated by the ITLB.
Data load
translation miss
01100
A data load translation miss exception is caused when an effective address for a data load
operation cannot be translated by the DTLB.
Data store
translation miss
01200
A data store translation miss exception is caused when an effective address for a data
store operation cannot be translated by the DTLB; or where a DTLB hit occurs, and the
change
Table 15.
Exceptions and Conditions (Continued)
Exception Type
Vector Offset
(hex)
Causing Conditions
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