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參數(shù)資料
| 型號(hào)： | TSPC603RVGU10LC |
| 元件分類： | 微處理器 |
| 英文描述： | MICROPROCESSOR|32-BIT|CMOS|BGA|255PIN|CERAMIC |
| 中文描述： | 微處理器| 32位|的CMOS | BGA封裝| 255PIN |陶瓷 |
| 文件頁數(shù)： | 35/42頁 |
| 文件大?。?/td> | 961K |
| 代理商： | TSPC603RVGU10LC |
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35
TSPC603R
2125A–12/01
The 603r also provides independent four-entry BAT arrays for instructions and data that main-
tain address translations for blocks of memory. These entries define blocks that can vary from
128K byte to 256M byte. The BAT arrays are maintained by system software.
As specified by the PowerPC architecture, the hashed page table is a variable-sized data
structure that defines the mapping between virtual page numbers and physical page numbers.
The page table size is a power of 2, and its starting address is a multiple of its size.
Also as specified by the PowerPC architecture, the page table contains a number of page
table entry groups (PTEGs). A PTEG contains eight page table entries (PTEs) of eight bytes
each; therefore, each PTEG is 64 bytes long. PTEG addresses are entry points for table
search operations.
Instruction Timing
The 603r is a pipelined superscalar processor. A pipelined processor is one in which the pro-
cessing of an instruction is reduced into discrete stages. Because the processing of an
instruction is broken into a series of stages, an instruction does not require the entire
resources of an execution unit. For example, after an instruction completes the decode stage,
it can pass on to the next stage, while the subsequent instruction can advance into the decode
stage. This improves the throughput of the instruction flow. For example, it may take three
cycles for a floating-point instruction to complete, but if there are no stalls in the floating-point
pipeline, a series of floating-point instructions can have a throughput of one instruction per
cycle.
The instruction pipeline in the 603r has four major pipeline stages, described a follows:
The fetch pipeline stage primarily involves retrieving instructions from the memory system
and determining the location of the next instruction fetch. Additionally, the BPU decodes
branches during the fetch stage and folds out branch instructions before the dispatch
stage if possible.
The dispatch pipeline stage is responsible for decoding the instructions supplied by the
instruction fetch stage, and determining which of the instructions are eligible to be
dispatched in the current cycle. in addition, the source operands of the instructions are
read from the appropriate register file and dispatched with the instruction to the execute
pipeline stage. At the end of the dispatch pipeline stage, the dispatched instructions and
their operands are latched by the appropriate execution unit.
During the execute pipeline stage each execution unit that has an executable instruction
executes the selected instruction (perhaps over multiple cycles), writes the instruction’s
result into the appropriate rename register, and notifies the completion stage that the
instruction has finished execution. In the case of an internal exception, the execution unit
reports the exception to the completion/writeback pipeline stage and discontinues
instruction execution until the exception is handled. The exception is not signaled until that
instruction is the next to be completed. Execution of most floating-point instructions is
pipelined within the FPU allowing up to three instructions to be executing in the FPU
concurrently. The pipeline stages for the floating-point unit are multiply, add, and
round-convert. Execution of most load/store instructions is also pipelined. The load/store
units has two pipeline stages. The first stage is for effective address calculation and MMU
translation and the second stage is for accessing the data in the cache.
The complete/writeback pipeline stage maintains the correct architectural machine state
and transfers the contents of the rename registers to the GPRs and FPRs as instructions
are retired. If the completion logic detects an instruction causing an exception, all following
instructions are cancelled, their execution results in rename registers are discarded, and
instructions are fetched from the correct instruction stream.
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| TSPC603RVGU12LC | 功能描述:IC MPU 32BIT 12MHZ 255CBGA RoHS:否 類別:集成電路 (IC) >> 嵌入式 - 微處理器 系列:- 標(biāo)準(zhǔn)包裝:60 系列:SCC 處理器類型:Z380 特點(diǎn):全靜電 Z380 CPU 速度:20MHz 電壓:5V 安裝類型:表面貼裝 封裝/外殼:144-LQFP 供應(yīng)商設(shè)備封裝:144-LQFP 包裝:托盤 |
| TSPC603RVGU14LC | 功能描述:IC MPU 32BIT 14MHZ 255CBGA RoHS:否 類別:集成電路 (IC) >> 嵌入式 - 微處理器 系列:- 標(biāo)準(zhǔn)包裝:60 系列:SCC 處理器類型:Z380 特點(diǎn):全靜電 Z380 CPU 速度:20MHz 電壓:5V 安裝類型:表面貼裝 封裝/外殼:144-LQFP 供應(yīng)商設(shè)備封裝:144-LQFP 包裝:托盤 |
| TSPC603RVGU6LC | 功能描述:IC MPU 32BIT 6MHZ 255CBGA RoHS:否 類別:集成電路 (IC) >> 嵌入式 - 微處理器 系列:- 標(biāo)準(zhǔn)包裝:60 系列:SCC 處理器類型:Z380 特點(diǎn):全靜電 Z380 CPU 速度:20MHz 電壓:5V 安裝類型:表面貼裝 封裝/外殼:144-LQFP 供應(yīng)商設(shè)備封裝:144-LQFP 包裝:托盤 |
| TSPC603RVGU8LC | 功能描述:IC MPU 32BIT 8MHZ 255CBGA RoHS:否 類別:集成電路 (IC) >> 嵌入式 - 微處理器 系列:- 標(biāo)準(zhǔn)包裝:60 系列:SCC 處理器類型:Z380 特點(diǎn):全靜電 Z380 CPU 速度:20MHz 電壓:5V 安裝類型:表面貼裝 封裝/外殼:144-LQFP 供應(yīng)商設(shè)備封裝:144-LQFP 包裝:托盤 |
| TSPC740A | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:TSPC750A/740A [Updated 3/02. 44 Pages] 32-bit RISC Microprocessor. 200-266 MHz |
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