- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄365988 > TSPC603RVGU8LC MICROPROCESSOR|32-BIT|CMOS|BGA|255PIN|CERAMIC PDF資料下載
參數(shù)資料
| 型號： | TSPC603RVGU8LC |
| 元件分類： | 微處理器 |
| 英文描述： | MICROPROCESSOR|32-BIT|CMOS|BGA|255PIN|CERAMIC |
| 中文描述： | 微處理器| 32位|的CMOS | BGA封裝| 255PIN |陶瓷 |
| 文件頁數(shù)： | 15/42頁 |
| 文件大小： | 961K |
| 代理商： | TSPC603RVGU8LC |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁當(dāng)前第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁
15
TSPC603R
2125A–12/01
Return to full-power mode after PLL and SYSCLK disabled in sleep mode:
- Enable SYSCLK.
- Reconfigure PLL into desired processor clock mode.
- System logic waits for PLL startup and relock time (100
μ
sec).
- System logic asserts one of the sleep recovery signals (for example, INT or SMI).
Power Management Software Considerations
Since the 603r is a dual issue processor with out-of-order execution capability, care must be
taken in how the power management mode is entered. Furthermore, nap and sleep modes
require all outstanding bus operations to be completed before the power management mode is
entered. Normally during system configuration time, one of the power management modes
would be selected by setting the appropriate HID0 mode bit. Later on, the power management
mode is invoked by setting the MSR[POW] bit. To provide a clean transition into and out of the
power management mode, the
stmsr
[POW] should be preceded by a
sync
instruction and fol-
lowed by an
isync
instruction.
Power Dissipation
Notes:
1. These values apply for all valid PLL_CFG[0-3] settings and do not include output driver power (OVDD) or analog supply
power (AV
DD
). OV
DD
power is system dependent but is typically
≤
10% of V
DD
. Worst-case AV
DD
= 15 mW.
2. Typical power is an average value measured at V
DD
= AV
DD
= 2.5V, OV
V
= 3.3V, in a system executing typical applications
and benchmark sequences.
3. Maximum power is measured at V
DD
= 2.625V using a worst-case instruction mix.
4. To calculate the power consumption at low temperature (-55°C),
use a factor of 1.25
.
Table 8.
Power Dissipation
V
dd
/A
V
dd
= 2.5
±
5%V dc, O
V
dd
= 3.3
±
5%V dc, GND = 0V dc, 0
°
C
≤
T
C
≤
125
°
C
CPU Clock Frequency
166 MHz
200 MHz
233 MHz
266 MHz
300 MHz
Units
Full-On Mode (DPM Enabled)
Typical
2.1
2.5
3.0
3.5
4.0
W
Max
3.2
4.0
4.6
5.3
6.0
W
Doze Mode
Typical
1.5
1.7
1.8
2.0
2.1
W
Nap Mode
Typical
100
120
140
160
180
mW
Sleep Mode
Typical
96
110
123
135
150
mW
Sleep Mode-PLL Disabled
Typical
60
60
60
60
60
mW
Sleep Mode-PLL and SYSCLK Disabled
Typical
25
25
25
25
25
mW
Maximum
60
60
60
80
100
mW
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| TSXPC603RMG10LC | MICROPROCESSOR|32-BIT|CMOS|BGA|255PIN|CERAMIC |
| TSXPC603RMG12LC | MICROPROCESSOR|32-BIT|CMOS|BGA|255PIN|CERAMIC |
| TSXPC603RMG14LC | MICROPROCESSOR|32-BIT|CMOS|BGA|255PIN|CERAMIC |
| TSXPC603RMG6LC | MICROPROCESSOR|32-BIT|CMOS|BGA|255PIN|CERAMIC |
| TSXPC603RMG8LC | MICROPROCESSOR|32-BIT|CMOS|BGA|255PIN|CERAMIC |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| TSPC740A | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:TSPC750A/740A [Updated 3/02. 44 Pages] 32-bit RISC Microprocessor. 200-266 MHz |
| TSPC750A | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:TSPC750A/740A [Updated 3/02. 44 Pages] 32-bit RISC Microprocessor. 200-266 MHz |
| TSPC750AMG10LE | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Microprocessor |
| TSPC750AMG10LH | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Microprocessor |
| TSPC750AMG12LE | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Microprocessor |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。