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參數(shù)資料
| 型號： | TSPC603RVGU8LC |
| 元件分類： | 微處理器 |
| 英文描述： | MICROPROCESSOR|32-BIT|CMOS|BGA|255PIN|CERAMIC |
| 中文描述： | 微處理器| 32位|的CMOS | BGA封裝| 255PIN |陶瓷 |
| 文件頁數(shù)： | 18/42頁 |
| 文件大?。?/td> | 961K |
| 代理商： | TSPC603RVGU8LC |
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18
TSPC603R
2125A–12/01
Table 11 provides the input AC timing specifications for the 603r as defined in Figure 6 and
Figure 7.
Notes:
1. All input specifications are measured from the TTL level (0.8 or 2.0V) of the signal in question to the 1.4V of the rising edge
of the input SYSCLK. Both input and output timings are measured at the pin. See Figure 7.
2. Address/data/transfer attribute input signals are composed of the following: A[0-31], AP[0-3], TT[0-4], TC[0-1], TBST,
TSIZ[0-2], GBL, DH[0-31], DL[0-31], DP[9-7].
3. All other input signals are composed of the following: TS, ABB, DBB, ARTRY, BG, AACK, DBG, DBWO, TA, DRTRY, TEA,
DBDIS, HRESET, SRESET, INT, SMI, MCP, TBEN, QACK, TLBISYNC.
4. The setup and hold time is with respect to the rising edge of HRESET. See Figure 7.
5. t
sysclk
is the period of the external clock (SYSCLK) in nanoseconds (ns). The numbers given in the table must be multiplied
by the period of SYSCLK to compute the actual time duration (in nanoseconds) of the parameter in question.
6. These values are guaranteed by design, and are not tested.
7. This specification is for configuration mode only. Also note that HRESET must be held asserted for a minimum of 255 bus
clocks after the PLL relock time (100 μs) during the power-on reset sequence.
Figure 6.
Input Timing Diagram
Table 11.
Input AC Timing Specifications
V
dd
= A
V
dd
= 2.5V
±
5%; O
V
dd
= 3.3
±
5%V dc, GND = 0V dc, -55
°
C
≤
T
C
≤
125
°
C
Num
Characteristics
166,200 MHz
233,266 MHz
300 MHz
Unit
Note
Min
Max
Min
Max
Min
Max
10a
Address/data/transfer attribute inputs valid to SYSCLK
(input setup)
2.5
-
2.5
-
2.5
-
ns
2
10b
All other inputs valid to SYSCLK (input setup)
4.0
-
3.5
-
3.5
-
ns
3
10c
Mode select inputs valid to HRESET (input setup) (for
DRTRY, QACK and TLBISYNC)
8
-
8
-
8
-
t
sysclk
4,5,6,
7
11a
SYSCLK to address/data/transfer attribute inputs invalid
(input hold)
1.0
-
1.0
-
1.0
-
ns
2
11b
SYSCLK to all other inputs invalid (input hold)
1.0
-
1.0
-
1.0
-
ns
3
11c
HRESET to mode select inputs invalid (input hold) (for
DRTRY, QACK, and TLBISYNC)
0
-
0
-
0
-
ns
4,6,7
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