31
TSPC750A/740A
2128A–HIREL–01/02
ClockRelationships
Choice
TheTSPC750A’sPLLisconfiguredbythePLL_CFG[0-3]signals.ForagivenSYSCLK
(bus)frequency,thePLLconfigurationsignalssettheinternalCPUandVCOfrequency
ofoperation.ThePLLconfigurationfortheTSPC750AisshowninTable16fornominal
frequencies.Table17providessamplecore-to-L2frequencies.
Table16.
TSPC750AMicroprocessorPLLConfiguration
Notes:
1. PLL_CFG[0—3]settingsnotlistedarereserved.
2. Thesamplebus-to-corefrequenciesshownareforreferenceonly.SomePLLconfigurationsmayselectbus,core,orVCO
frequencieswhicharenotuseful,notsupported,ornottestedforbytheTSPC750A;see“ClockACSpecifications,”forvalid
SYSCLKandVCOfrequencies.
3. InPLL-bypassmode,theSYSCLKinputsignalclockstheinternalprocessordirectly,thePLLisdisabled,andthebusmode
issetfor1:1modeoperation.Thismodeisintendedforfactoryuseonly.
Note:TheACtimingspecificationsgiveninthisdocumentdonotapplyinPLL-bypassmode
.
4. Inclock-offmode,noclockingoccursinsidetheTSPC750AregardlessoftheSYSCLKinput.
PLL_CFG
[0-3]
SampleBus-to-CoreFrequencyinMHz(VCOFrequencyinMHz)
Bus-to-
Core
Multiplier
Core-to
VCO
Multiplier
Bus25
MHz
Bus
33.3
MHz
Bus40
MHz
Bus50
MHz
Bus
66.6
MHz
Bus75
MHz
Bus
83.3
MHz
Bus
100
MHz
1000
3x
2x
150
(300)
200
(400)
225
(450)
250
(500)
1110
3.5x
2x
175
(350)
233
(466)
262
(525)
1010
4x
2x
160
(320)
200
(400)
266
(533)
0111
4.5x
2x
150
(300)
180
(360)
225
(450)
1011
5x
2x
166
(333)
200
(400)
250
(500)
1001
5.5x
2x
183
(366)
220
(440)
1101
6x
2x
150
(300)
200
(400)
240
(480)
0101
6.5x
2x
162
(325)
216
(433)
260
(520)
0010
7x
2x
175
(350)
233
(466)
0001
7.5x
2x
187
(375)
250
(500)
1100
8x
2x
200
(400)
266
(533)
0011
PLLoff/bypass
PLLoff,SYSCLKclockscorecircuitrydirectly,1xbus-to-coreimplied
1111
PLLoff
PLLoff,nocoreclockingoccurs