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參數(shù)資料
| 型號： | TSPC750AVG10LH |
| 英文描述： | Microprocessor |
| 中文描述： | 微處理器 |
| 文件頁數(shù)： | 21/44頁 |
| 文件大?。?/td> | 870K |
| 代理商： | TSPC750AVG10LH |
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21
TSPC750A/740A
2128A–HIREL–01/02
Notes:
1. For60xbussignals,thereferenceisOV
DD
whileL2OV
DD
isthereferencefortheL2bussignals.
2. Excludestestsignals(LSSD_MODE,L1_TSTCLK,L2_TSTCLK)andIEEE1149.1boundaryscan(JTAG)signals.
3. Capacitanceisperiodicallysampledratherthan100%tested.
4. TheleakageismeasuredfornominalOV
DD
andV
DD
,orbothOV
DD
andV
DD
mustvaryinthesamedirection(forexample,
bothOV
DD
andV
DD
varybyeither+5%or-5%).
DynamicCharacteristics
Afterfabrication,partsaresortedbymaximumprocessorcorefrequencyasshownin
“ClockACSpecifications”andtestedforconformancetotheACspecificationsforthat
frequency.Thesespecificationsarefor200,233,and266MHzprocessorcorefrequen-
cies.Theprocessorcorefrequencyisdeterminedbythebus(SYSCLK)frequencyand
thesettingsofthePLL_CFG[0-3]signals.Partsaresoldbymaximumprocessorcore
frequency.
ClockACSpecifications
Table9providestheclockACtimingspecificationsasdefinedinFigure9.
Notes:
1.
Caution
:TheSYSCLKfrequencyandPLL_CFG[0-3]settingsmustbechosensuchthattheresultingSYSCLK(bus)fre-
quency,CPU(core)frequency,andPLL(VCO)frequencydonotexceedtheirrespectivemaximumorminimumoperating
frequencies.RefertothePLL_CFG[0-3]signaldescriptionin“PLLConfiguration,”forvalidPLL_CFG[0-3]settings
2. RiseandfalltimesfortheSYSCLKinputaremeasuredfrom0.4to2.4V.
3. Timingisguaranteedbydesignandcharacterization.
4. Thetotalinputjitter(shorttermandlongtermcombined)mustbeunder
±
150ps.
5. Relocktimingisguaranteedbydesignandcharacterization.PLL-relocktimeisthemaximumamountoftimerequiredfor
PLLlockafterastableV
DD
andSYSCLKarereachedduringthepower-onresetsequence.Thisspecificationalsoapplies
whenthePLLhasbeendisabledandsubsequentlyre-enabledduringsleepmode.AlsonotethatHRESETmustbeheld
assertedforaminimumof255busclocksafterthePLL-relocktimeduringthepower-onresetsequence.
SYSCLKInputLowVoltage
CV
IL
GND
0.4
V
InputLeakageCurrent,V
IN
=OV
DD
I
in
-
30
μA
1,2
Hi-Z(off-state)LeakageCurrent,V
IN
=OV
DD
I
TSI
-
30
μA
1,2,4
OutputHighVoltage,I
OH
=
-6mA
V
OH
2.4
-
V
OutputLowVoltage,I
OL
=6mA
V
OL
-
0.4
V
Capacitance,V
IN
=0V,f=1MHz
C
in
-
5.0
pF
2,3
Table8.
DCElectricalSpecifications
V
DD
=AV
DD
=L2AV
DD
=2.6V
DC
±
100mV,OV
DD
=L2OV
DD
=3.3±
5%V
DC
,GND=0V
DC
,-55
≤
T
j
<125
°
C
Characteristic
Symbol
Min
Max
Unit
Notes
Table9.
ClockACTimingSpecifications
V
DD
=AV
DD
=L2AV
DD
=2.6V
DC
±
100mV,OV
DD
=L2OV
DD
=3.3±5%V
DC
,GND=0V
DC
,-55
≤
T
j
<125
°
C
Num
Characteristic
200MHz
233MHz
266MHz
Unit
Notes
Min
Max
Min
Max
Min
Max
ProcessorFrequency
150
200
150
233
150
266
MHz
VCOFrequency
300
400
300
466
300
533
MHz
SYSCLKFrequency
25
83.3
25
83.3
25
83.3
MHz
1
1
SYSCLKCycleTime
12
40
12
40
12
40
ns
2,3
SYSCLKRiseandFallTime
-
2
-
2
-
2
ns
2
4
SYSCLKDutyCycleMeasuredat1.4V
40
60
40
60
40
60
%
3
SYSCLKJitter
-
±
150
-
±
150
-
±
150
ps
4
InternalPLLRelockTime
-
100
-
100
-
100
μs
5
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