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參數(shù)資料
| 型號： | TSRD1003G |
| 元件分類： | 通信、網(wǎng)絡(luò)模塊及開發(fā)工具 |
| 英文描述： | Telecomm/Datacomm |
| 中文描述： | 電信/數(shù)據(jù)通信 |
| 文件頁數(shù)： | 2/4頁 |
| 文件大小： | 59K |
| 代理商： | TSRD1003G |
Product Brief
February 2002
~1.06—3.2 Gbits/s Serializer and Deserializer (Macro)
TSRD1003G
2
Agere Systems Inc.
Channels
I
10 TxRx pairs maximum per macro.
I
User-selectable from 6—10 channels by eliminating
or selectively powering-off unnecessary blocks.
Modular Macrocell
I
The macrocell consists of three smaller blocks as fol-
lows:
— PLL.
— Transmit channel block (TX).
— Receiver channel block (RX).
I
Four different configurations as follows:
— Ten RX blocks and one PLL.
— Ten TX blocks and one PLL.
— Ten RX/TX block pairs and one PLL.
— One TX block and one PLL.
Interfaces
I
High speed: current mode logic (CML). LVDS and
LVPECL compatibility is available with off-chip com-
ponents.
I
Parallel data: CMOS selectable between a 16-bit or
20-bit parallel I/O.
I
Registers and control logic: a four-line serial inter-
face, allowing each channel to be addressed individ-
ually with minimal routing.
Power Consumption
I
105 mW per channel (typical, including common cir-
cuitry) consumed when all 10 channels are operat-
ing.
I
If less than 10 channels are operating, the power
consumption per channel increases to include more
of the common circuitry.
Independent Powerdown
I
Independent user-selectable powerdown of the fol-
lowing:
— CML buffers.
— Individual transmit blocks.
— Individual receive blocks.
— Transmit low-speed clock generation.
— PLL.
Reset
I
Resets any macro or any RX/TX block within the
device.
I
Includes a power-on reset circuit within the macros.
This circuit is used solely to reset the SERDES
blocks within a macro after a powerup event. (No
external access to the output of this circuit is pro-
vided.)
PLL (Phase-Locked Loop)
I
The PLL is based on a differential ring oscillator at
half of the intended data rate.
I
The synthesized frequency can be programmed to
either 8X or 10X the reference frequency.
I
PLL relock without reset: the PLL can relock without
requiring a reset (for example, after switching refer-
ence clocks).
I
A PLL lock indicator is provided.
Transmitter
I
Each transmit (TX) block serializes a parallel data
word with a width of 16 bits or 20 bits depending on
the control register setting.
I
The TX block transforms the parallel input word into
a serial data stream by using a high-speed clock that
is synthesized from the reference clock by the PLL.
Transmit Pre-Emphasis
I
The transmit block output buffer can be programmed
through the serial register interface to select between
no pre-emphasis, a 12.5% level, or a 25% level.
I
Pre-emphasis boosts the high frequencies in the
transmitted data to compensate for losses present in
backplanes, thus extending the useful range of trans-
mission.
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