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參數(shù)資料
| 型號： | TSRD1003G |
| 元件分類： | 通信、網(wǎng)絡(luò)模塊及開發(fā)工具 |
| 英文描述： | Telecomm/Datacomm |
| 中文描述： | 電信/數(shù)據(jù)通信 |
| 文件頁數(shù)： | 3/4頁 |
| 文件大?。?/td> | 59K |
| 代理商： | TSRD1003G |
Product Brief
February 2002
~1.06—3.2 Gbits/s Serializer and Deserializer (Macro)
TSRD1003G
Agere Systems Inc.
3
Half Amplitude Output
I
The TX block output buffer can be programmed
through the serial interface to provide either of two
different levels of output amplitude, full or half.
I
The half amplitude mode allows chip-to-chip applica-
tions and other less stringent applications to reduce
the power consumption.
Skew Between Blocks
I
The skew will be less than 1.25 UI between transmit
blocks if the blocks are within a macro or within an
adjacent macro and use the same reference clock
with a maximum skew of 100 ps (±50 ps) between
macros.
Receiver
I
The receive (RX) block transforms a high-speed
serial bit stream into a stream of parallel words and
recovers a high-speed clock from the serial data.
I
The receive (RX) block further divides this clock
down to provide a clock that has a frequency equal
to the parallel word rate and that is phase-aligned to
the word boundary.
I
The CDR block that forms the core of the receiver is
a proprietary design which results in significant
power and area savings.
Loss of Signal and Signal Level
Detector
I
Simple analog loss-of-signal detector with a fixed
threshold between a 100 mVp-p differential and
175 mVp-p differential.
Automatic Lock-To Reference
I
The receive CDR automatically locks to reference in
the absence of receive data. When a loss-of-signal is
indicated, the reference clock bit is automatically
switched to the RX serial inputs (this can also be dis-
abled by setting a bit in the serial control I/F).
I
The receiver can also be forced to lock-to reference
by setting a bit in the serial control I/F.
Loss of Reference Clock
I
If the reference clock (REFCLK) bit is lost, the VCO
in the PLL is forced to its lowest frequency.
I
An alarm bit in the PLL status register indicates this
condition. This condition is also indicated by the core
output signals of the PLL.
High-Speed Clock Output
I
A clock at a 1/8 or 1/10 data rate from both the trans-
mitter and the receiver blocks is provided to circuitry
outside the macrocell.
Testability Features
I
Allows testability within the ASIC.
I
Test modes are not encoded, allowing mixing and
matching of test modes.
I
Self-synchronizing PRBS compatible with
Agilent
and
Anritsu
bit error rate test systems.
I
Internal loopback for parallel and serial data for TxRx
macro option.
I
Independent transmit and receive built-in self-test.
Digital Library Interface
I
Standard digital library interface allowing digital
blocks from the Agere library or custom blocks to be
integrated into the device.
I
Examples include PRBS, link state machine, SONET
framer, 8B/10B encoder, 64/66 encoder, byte aligner,
custom blocks.
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