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參數(shù)資料
| 型號(hào)： | TSXPC603RVGSU14LC |
| 英文描述： | MICROPROCESSOR|32-BIT|CMOS|BGA|255PIN|CERAMIC |
| 中文描述： | 微處理器| 32位|的CMOS | BGA封裝| 255PIN |陶瓷 |
| 文件頁(yè)數(shù)： | 25/42頁(yè) |
| 文件大?。?/td> | 961K |
| 代理商： | TSXPC603RVGSU14LC |
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25
TSPC603R
2125A–12/01
The required physical address (RPA) register is loaded by the processor with the second
word of the correct PTE during a page table search.
The hardware implementation (HID0 and HID1) registers provide the means for enabling
the 603r’s checkstops and features, and allows software to read the configuration of the
PLL configuration signals.
The instruction address breakpoint register (IABR) is loaded with an instruction address
that is compared to instruction addresses in the dispatch queue. When an address match
occurs, an instruction address breakpoint exception is generated.
Figure 13 shows all the 603r registers available at the user and supervisor level. The number
to the right of the SPRs indicate the number that is used in the syntax of the instruction oper-
ands to access the register.
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