參數(shù)資料
型號(hào)： TSXPC603RVGSU14LC
英文描述： MICROPROCESSOR|32-BIT|CMOS|BGA|255PIN|CERAMIC
中文描述： 微處理器| 32位|的CMOS | BGA封裝| 255PIN |陶瓷
文件頁(yè)數(shù)： 31/42頁(yè)
文件大?。?/td> 961K
代理商： TSXPC603RVGSU14LC
31
TSPC603R
2125A–12/01
Unless a catastrophic causes a system reset or machine check exception, only one exception
is handled at a time. If, for example, a single instruction encounters multiple exception condi-
tions, those conditions are encountered sequentially. After the exception handler handles an
exception, the instruction execution continues until the next exception condition is encoun-
tered. However, in many cases there is no attempt to re-execute the instruction. This method
of recognizing and handling exception conditions sequentially guarantees that exceptions are
recoverable.
Exception handlers should save the information stored in SRR0 and SRR1 early to prevent the
program state from being lost due to a system reset and machine check exception or to an
instruction-caused exception in the exception handler, and before enabling external interrupts.
The PowerPC architecture support four types of exceptions:
Synchronous, precise
- These are causes by instructions. All instruction-caused
exceptions are handled precisely; that is, the machine state at the time the exception
occurs is known and can be completely restored. This means that (excluding the trap and
system call exceptions) the address of the faulting instruction is provided to the exception
handler and that neither the faulting instruction nor subsequent instructions in the code
stream will complete execution before the exception is taken. Once the exception is
processed, execution resumes at the address of the faulting instruction (or at an alternate
address provided by the exception handler). When an exception is taken due to an trap or
system call instruction, execution resumes at an address provided by the handler.
Synchronous, imprecise
- The PowerPC architecture defines two imprecise
floating-point exception modes, recoverable and nonrecoverable. Even though the 603r
provides a means to enable he imprecise modes, it implements these modes identically to
the precise mode (-hat is, all enabled floating-point enabled exceptions are always precise
on the 603r).
Asynchronous, maskable
- The external, SMI, and decrementer interrupts are maskable
asynchronous exceptions. When these exceptions occur, their handling is postponed until
the next instruction, and any exceptions associated with that instruction, completes
execution. If there are no instructions in the execution units, the exception is taken
immediately upon determination of the correct restart address (for loading SRR0).
Asynchronous, non maskable
- There are two non maskable asynchronous exceptions:
system reset and the machine check exception. These exceptions may not be
recoverable, or may provide a limited degree of recoverability. All exceptions report
recoverability through the SMR[RI] bit.
PowerPC 603r Microprocessor Exception Model
A specified by the PowerPC architecture, all 603r exceptions can be described as either pre-
cise or imprecise and either synchronous or asynchronous. Asynchronous exceptions (some
or which are maskable) are caused by events external to the processor’s execution; synchro-
nous exceptions, which are all handled precisely by the 603r, are caused by instructions. The
603r exception classes are shown in Table 14.
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