參數(shù)資料
型號: TTSI2K32T3BAL
英文描述: 2048-Channel, 32-Highway Time-Slot Interchanger
中文描述: 2048通道,32道時隙交換器
文件頁數(shù): 60/66頁
文件大?。?/td> 1321K
代理商: TTSI2K32T3BAL
TTSI2K32T
2048-Channel, 32-Highway Time-Slot Interchanger
Preliminary Data Sheet
February 1999
60
Lucent Technologies Inc.
Timing Characteristics
(continued)
Table 49. Synchronous Microprocessor Interface Timing
* The CS setup timing requirement relative to PCLK can be programmed for either the first or second clock cycle of a microprocessor access
using CSV (bit 7) of the general command register.
The input setup timing requirement assumes a PCLK frequency of at least 25 MHz. For frequencies slower than 25 MHz, the D[7—0] propa-
gation delay must be less than 40 ns from the rising edge of PCLK which samples AS.
When data is driven by the TSI during a synchronous read cycle, good data is driven prior to DT being asserted.
Symbol
Description
Min
Max
Unit
t15
t16
t17
t18
t19
t20
t21
t22
t23
t24
t25
CS Setup to Rising PCLK Edge
CS Hold from Rising PCLK Edge
AS Setup to Rising PCLK Edge
AS Hold from Rising PCLK Edge
R/W, A[14—0] Input Setup to Rising PCLK Edge
D[7—0] Input Setup to Rising PCLK Edge
R/W, A[14—0], D[7—0] Input Hold from Rising PCLK Edge
DT Output Delay from Rising PCLK Edge (C
L
= 10 pF to 50 pF)
DT High Impedance from Falling PCLK Edge (C
L
= 50 pF)
D[7—0] Output Delay from Rising PCLK Edge (C
L
= 50 pF)
D[7—0] Output High Impedance from Rising PCLK Edge
(C
L
= 10 pF to 50 pF)
10*
0
6
0
0
0
0
2.6
4
10
7
0
12
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
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