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參數(shù)資料
| 型號： | TUA4401K |
| 廠商： | INFINEON TECHNOLOGIES AG |
| 元件分類： | 接收器 |
| 英文描述： | FM, AUDIO SINGLE CHIP RECEIVER, PQFP44 |
| 封裝： | MQFP-44 |
| 文件頁數(shù)： | 36/41頁 |
| 文件大小： | 990K |
| 代理商： | TUA4401K |
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Reference
5 - 14
TUA 4401K
Wireless Components
Specification, 17.02.00
2)C
b= capacitance of one bus line in pF.
Note that the maximum tF for the SDA and SCL bus lines quoted at 300ns is
longer than the specified maximum tOF for the output stages (250ns).This
allows series protection resistors to be connected between the SDA / SCL pins
and the SDA /SCL bus lines without exceeding the maximum specified tF.
Table 5-4
Parameter
Symbol
min
max
Unit
LOW level input voltage (SDA, SCL)
VIL
-0.5
0.90
V
HIGH level input voltage (SDA, SCL)
VIH
2.10
5.50
V
Pulse width of spikes which must be suppressed by the input fil-
ter
tSP
0
50
ns
LOW level output voltage 3mA sink current (SDA)
VOL
0
0.40
V
Output fall time from VIHmin to VILmax with a bus capacitance
from 10pF to 400pFwith up to 3mA
tOF
20+0.1Cb
2)
250
ns
SCL clock frequency
fSCL
0
400
kHz
Bus free time between a STOP and START condition
tBUF
1.3
s
Hold time (repeated) START condition. After this period, the first
clock pulse is generated.
tHO.STA
0.6
s
LOW period of the SCL clock
tLOW
1.3
s
HIGH period of the SCL clock
tHIGH
0.6
s
Set-up time for a repeated START condition
tSU.STA
0.6
s
Data hold time
tHD.DAT
0
ns
Data set -up time
tSU.DAT
100
ns
Rise, fall time of both SDA and SCL signals
tR, tF
20+0.1Cb
2)
300
ns
Set-up time for STOP condition
tSU.STO
0.6
s
Capacitive load for each bus line
Cb
400
pF
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相關代理商/技術參數(shù) |
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