2
–
2
2.1.1
Video Input Selection
The TVP5145 device has three analog channels that accept six ac-coupled video inputs. The internal video
multiplexers can be configured via the host port. The six analog video inputs may be connected as one of the following:
Two selectable analog YPbPr component video inputs
One selectable analog YPbPr component video, one selectable S-video, and one composite video inputs
Six selectable individual composite video inputs
Two selectable S-video input and two composite video inputs
The input selection is done by the register setup (see Section 2.12.1,
Video Input Source Selection #1
).
2.1.2
Analog Input Clamping and Automatic Gain Control Circuits
An internal clamping circuit restores the ac-coupled video signal to a fixed dc level. The clamping circuit provides
line-by-line restoration of the video sync level to a fixed dc reference voltage. Two modes of clamping are provided,
coarse and fine. In coarse mode, the most negative portion of the input signal (typically the sync tip) is clamped to
a fixed dc level. Fine clamp mode may be enabled to prevent spurious level shifting caused by noise more negative
than the sync tip on the input signal. If fine clamp mode is selected, clamping is only enabled during the sync period.
External capacitors of 0.1
μ
F on terminals 2 (CLAMP1) and 13 (CLAMP2) are required.
The input video signal amplitude may vary significantly from the nominal level of 1 V
P-P
. An automatic gain control
circuit (AGC) adjusts the signal amplitude to utilize the maximum range of the A/D converter without clipping. The
AGC adjusts gain to achieve desired sync amplitude. Some nonstandard video signals contain peak white levels that
saturate the A/D converter. In these cases, the AGC automatically cuts back gain to avoid clipping. The AGC has a
range of
–
3 dB to 6 dB.
The fine gain and offset adjustment block precisely controls the sync tip and back porch levels to achieve the best
linearity performance.
2.1.3
A/D Converters
The TVP5145 device contains two 10-bit oversampling A/D converters that digitize the analog video inputs. A/D
converter reference voltages on terminals 8 (REFP) and 7 (REFM) require an external capacitor network for filtering,
as shown in Figure 2
–
1.
2.2
Digital Processing
Figure 2
–
2 is a block diagram of the TVP5145 digital video decoder processing. This block receives digitized video
signals from the A/D converters and performs Y/C separation, and Y, U/V signal enhancements. It also generates
horizontal and vertical syncs. The Y U/V digital output may be programmed into various formats: 20-/16-bit or 10-/8-bit
4:2:2, and 10-/8-bit ITU-R BT.656 parallel interface standard. This circuit also detects copy-protected material
according to the Macrovision specification, and retrieves VBI information. S-video and component video bypass the
Y/C separation block.