參數(shù)資料
型號(hào): TVP5154AIPNP
廠(chǎng)商: Texas Instruments
文件頁(yè)數(shù): 19/93頁(yè)
文件大小: 0K
描述: IC VIDEO DECODER 4CH 128-HTQFP
產(chǎn)品培訓(xùn)模塊: Data Converter Basics
標(biāo)準(zhǔn)包裝: 90
類(lèi)型: 視頻解碼器
應(yīng)用: 安全系統(tǒng)
電壓 - 電源,模擬: 1.8V
電壓 - 電源,數(shù)字: 1.8V,3.3V
安裝類(lèi)型: 表面貼裝
封裝/外殼: 128-TQFP 裸露焊盤(pán)
供應(yīng)商設(shè)備封裝: 128-HTQFP(14x14)
包裝: 托盤(pán)
產(chǎn)品目錄頁(yè)面: 887 (CN2011-ZH PDF)
配用: TVP5154EVM-ND - TVP5154EVM
296-23058-ND - EVAL MODULE FOR DM642
其它名稱(chēng): 296-23153
SLES214C – DECEMBER 2007 – REVISED SEPTEMBER 2010
www.ti.com
7
Internal Control Registers
7.1
Overview
The TVP5154A decoder is initialized and controlled by sets of internal registers that set all device
operating parameters. Communication between the external controller and the TVP5154A decoder is
through the I2C. Two sets of registers exist, direct and indirect. Table 7-1 shows the summary of the direct
registers. Reserved registers must not be written. Reserved bits in the defined registers must be written
with zeros, unless otherwise noted. The detailed programming information of each register is described in
the following sections.
I2C register FEh controls which of the four decoders receives I2C commands. I2C register FFh controls
which decoder core responds to I2C reads. Note, for a read operation, it is necessary to perform a write
first, to set the desired sub-address for reading.
After power up and the hardware reset, each decoder must be started by writing 00h to register 7Fh for all
four decoders.
Table 7-1. Direct Register Summary
REGISTER FUNCTION
ADDRESS
DEFAULT
R/W(1)
Video input source selection #1
00h
R/W
Analog channel controls
01h
15h
R/W
Operation mode controls
02h
00h
R/W
Miscellaneous controls
03h
01h
R/W
Autoswitch mask
04h
DCh
R/W
Clock control
05h
08h
R/W
Color killer threshold control
06h
10h
R/W
Luminance processing control #1
07h
60h
R/W
Luminance processing control #2
08h
00h
R/W
Brightness control
09h
80h
R/W
Color saturation control
0Ah
80h
R/W
Hue control
0Bh
00h
R/W
Contrast control
0Ch
80h
R/W
Outputs and data rates select
0Dh
47h
R/W
Luminance processing control #3
0Eh
00h
R/W
Configuration shared pins
0Fh
08h
R/W
Reserved
10h
Active video cropping start MSB for unscaled data
11h
00h
R/W
Active video cropping start LSB for unscaled data
12h
00h
R/W
Active video cropping stop MSB for unscaled data
13h
00h
R/W
Active video cropping stop LSB for unscaled data
14h
00h
R/W
Genlock/RTC
15h
01h
R/W
Horizontal sync start
16h
80h
R/W
Ancillary SAV/EAV control
17h
52h
R/W
Vertical blanking start
18h
00h
R/W
Vertical blanking stop
19h
00h
R/W
Chrominance processing control #1
1Ah
0Ch
R/W
Chrominance processing control #2
1Bh
14h
R/W
Interrupt reset register B
1Ch
00h
R/W
Interrupt enable register B
1Dh
00h
R/W
(1)
R = Read only, W = Write only, R/W = Read and write
26
Internal Control Registers
Copyright 2007–2010, Texas Instruments Incorporated
Product Folder Link(s): TVP5154A
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