
Unscaled Data 1
Y/C & Syncs
CLK
Unscaled Data 2
Scaled Data 1
Scaled Data 2
t13
t14
t15
t16
t10
t11
t12
VC1
(SDA)
t1
t3
t7
t6
t8
t5
t2
t3
VC0
(SCL)
Data
Stop
Start
Stop
t4
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SLES214C – DECEMBER 2007 – REVISED SEPTEMBER 2010
Figure 9-3. Output Mode 3: Clock, Video Data, and Sync (Positive Edge Clock)
9.6
I
2C Host Port Timing
PARAMETER
TEST CONDITIONS
MIN
MAX
UNIT
t1
Bus free time, between STOP and START
1.3
s
t2
Setup time, (repeated) START condition
0.6
s
t3
Hold time, (repeated) START condition
0.6
s
t4
Setup time, STOP condition
0.6
ns
t5
Data setup time
100
ns
t6
Data hold time
0
0.9
s
t7
Rise time, VC1(SDA) and VC0(SCL) signal
Specified by design
250
ns
t8
Fall time, VC1(SDA) and VC0(SCL) signal
Specified by design
250
ns
Cb
Capacitive load for each bus line
Specified by design
400
pF
fI2C
I2C clock frequency
400
kHz
Figure 9-4. I2C Host Port Timing
9.7
Thermal Specifications
PARAMETER
TEST CONDITIONS(1)
MIN
TYP
MAX
UNIT
qJA
Junction-to-ambient thermal resistance, still air
Thermal pad soldered to 4-layer
17.17
°C/W
High-K PCB
qJC
Junction-to-case thermal resistance, still air
Thermal pad soldered to 4-layer
0.12
°C/W
High-K PCB
TJ(MAX)
Maximum junction temperature for reliable operation
105
°C
(1)
The exposed thermal pad must be soldered to a JEDEC High-K PCB with adequate ground plane.
Copyright 2007–2010, Texas Instruments Incorporated
Electrical Specifications
85