參數(shù)資料
型號(hào)： TVP7002PZPR
廠商： TEXAS INSTRUMENTS INC
元件分類(lèi)： 消費(fèi)家電
英文描述： SPECIALTY CONSUMER CIRCUIT, PQFP100
封裝： GREEN, PLASTIC, HTQFP-100
文件頁(yè)數(shù)： 44/57頁(yè)
文件大?。?/td> 517K
代理商： TVP7002PZPR
SLES206B
– MAY 2007 – REVISED MAY 2011
AVID Stop Pixel
Subaddress
42h
–43h
Default (062Ch)
Subaddress
7
6
5
4
3
2
1
0
42h
AVID stop [7:0]
43h
Reserved
AVID stop [12:8]
AVID stop [12:0]: AVID stop pixel number. The number of pixels of active video must be an even number. This is an absolute pixel location
from the leading edge of HSYNC (start pixel 0).
The TVP7002 updates the AVID Stop only when the AVID Stop MSB byte is written to.
AVID stop pixel register also controls the position of EAV code.
VBLK Field 0 Start Line Offset
Subaddress
44h
Default (05h)
7
6
5
4
3
2
1
0
VBLK start 0 [7:0]
VBLK start 0 [7:0]: VBLK start line offset for field 0 relative to the leading edge of VSYNC. The VBLK start line offset value affects the
location of transitions on the embedded sync V-bit and VBLK of the Data Enable output, but not the VSYNC output (VSOUT). Unsigned
integer.
VBLK Field 1 Start Line Offset
Subaddress
45h
Default (05h)
7
6
5
4
3
2
1
0
VBLK start 1 [7:0]
VBLK start 1 [7:0]: VBLK start line offset for field 1 relative to the leading edge of VSYNC. The VBLK start line offset value affects the
location of transitions on the embedded sync V-bit and VBLK of the Data Enable output, but not the VSYNC output (VSOUT). Unsigned
integer.
VBLK Field 0 Duration
Subaddress
46h
Default (1Eh)
7
6
5
4
3
2
1
0
VBLK duration 0 [7:0]
VBLK duration 0 [7:0]: VBLK duration in lines for field 0.
VBLK Field 1 Duration
Subaddress
47h
Default (1Eh)
7
6
5
4
3
2
1
0
VBLK duration 1 [7:0]
VBLK duration 1 [7:0]: VBLK duration in lines for field 1.
F-bit Field 0 Start Line Offset
Subaddress
48h
Default (00h)
7
6
5
4
3
2
1
0
F-bit start 0 [7:0]
F-bit start 0 [7:0]: F-bit Field 0 start line offset relative to the leading edge of VSYNC, signed integer, set F-bit to 0 until field 1 start line, it
only applies in interlaced mode. For a non-interlace mode, F-bit is always set to 0.
NOTE: The field ID output (FIDOUT) is always aligned with the leading edge of the VSYNC output (VSOUT).
Copyright
2007–2011, Texas Instruments Incorporated
49
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