參數(shù)資料
型號(hào)： TWL1110GQE
廠商： TEXAS INSTRUMENTS INC
元件分類： 消費(fèi)家電
英文描述： SPECIALTY CONSUMER CIRCUIT, PBGA80
封裝： PLASTIC, MICRO, BGA-80
文件頁(yè)數(shù)： 19/37頁(yè)
文件大?。?/td> 496K
代理商： TWL1110GQE
TWL1110
VOICE-BAND AUDIO PROCESSOR (VBAP
)
SLWS103 – NOVEMBER 2000
26
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
PRINCIPLES OF OPERATION
buzzer logic section
The single-ended output BUZZCON is a PDM signal intended to drive a buzzer through an external driver
transistor. The PDM begins as a selected DTMF tone, generated and passed through the receive D/A channel
and fed back to the transmit channel analog modulator, where a PDM signal is generated and routed to the
BUZZCON output.
Buzzcon
DTMF
Gain
Mux
Digital
Modulator
and
Filter
Analog
Modulator
Buzzer
Control
Figure 7. Buzzer Driver System Architecture
support section
The clock generator and control circuit use the master clock input (MCLK) to generate internal clocks to drive
internal counters, filters, and convertors. Register control data is written into and read back from the VBAP
registers via the control interface.
I2C- bus protocols
The VBAP serial interface is designed to be I2C bus-compatible and operates in the slave mode when CE is
high. This interface consists of the following terminals:
SCL:
I2C-bus serial clock—This input synchronizes the control data transfer to and from the codec.
SDA:
I2C-bus serial address/data input/output—This is a bidirectional terminal that transfers register
control addresses and data into and out of the codec. It is an open drain terminal and therefore
requires a pullup resistor to VCC (typical 10 k for 100 kHz).
TWL1110 has a fixed device select address of (E2)HEX for write mode and (E3)HEX for read mode.
For normal data transfer, SDA is allowed to change only when SCL is low. Changes when SCL is high are
reserved for indicating the start and stop conditions.
Data transfer may be initiated only when the bus is not busy. During data transfer, the data line must remain
stable whenever the clock line is at high. Changes in the data line while the clock line is at high are interpreted
as a start or stop condition.
Table 8. I2C-Bus Conditions
CONDITION
STATUS
DESCRIPTION
A
Bus not busy
Both data and clock lines remain at high.
B
Start data transfer
A high to low transition of the SDA line while the clock (SCL) is high determines a start condition.
All commands must proceed from a start condition.
C
Stop data transfer
A low to high transition of the SDA line while the clock (SCL) is high determines a stop condition.
All operations must end with a stop condition.
D
Data valid
The state of the data line represents valid data when, after a start condition, the data line is stable
for the duration of the high period of the clock signal.
The data on the line must be changed during the low period of the clock signal. There is one clock pulse per
bit of data.
相關(guān)PDF資料
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
TWL1110GQER 制造商:Texas Instruments 功能描述:VOICE BAND AUD PROCESSOR 80BGA MICROSTAR JUNIOR - Tape and Reel
TWL1110PBS 制造商:Rochester Electronics LLC 功能描述:- Bulk
TWL1110PBSR 制造商:Rochester Electronics LLC 功能描述:- Bulk
TWL1110TQFP 制造商:TI 制造商全稱:Texas Instruments 功能描述:VOICE-BAND AUDIO PROCESSOR VBAPE
TWL1200 制造商:TI 制造商全稱:Texas Instruments 功能描述:SDIO, UART, AND AUDIO VOLTAGE-TRANSLATION TRANSCEIVER
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