參數(shù)資料
型號： TZA1047HL/M1B
廠商： NXP SEMICONDUCTORS
元件分類： 消費家電
英文描述： SPECIALTY CONSUMER CIRCUIT, PQFP64
封裝： 10 X 10 MM, 1.4 MM HEIGHT, PLASTIC, MS-026, SOT314-2, LQFP-64
文件頁數(shù)： 11/69頁
文件大?。?/td> 324K
代理商： TZA1047HL/M1B
9397 750 14664
Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet
Rev. 02 — 1 June 2005
19 of 69
Philips Semiconductors
TZA1047
Preprocessor IC for CD and DVD rewritable
The DPD circuit is enabled by control bit DPD. If DPD = 0 the entire circuit is switched off
to reduce power dissipation in applications where DPD is not used.
The four input signals VUA to VUD, generated in the Input circuit, correspond to the
signals from the four central segments of the PDIC. There are four possible DPD methods
available DTD4, DTD4a, DTD2a or DTD2 which are specied by bits PD1, PD2 and
DTDC/I. The relationship between signals VUA to VUD and signals s1 to s4 for each DPD
method is shown in Table 6.
The signals VUA to VUD are fed through a low-pass lter LPF1 to lter out noise, then
through a high-pass lter (HPF) to remove the DC content and nally through a lead
network (equalizer) to boost the I3 amplitude. The cut-off frequency of LPF1 is controlled
via I2C-bus word FDPD[1:0] while the lead lter is controlled by word FLL[1:0]. The
selected signals s1 to s4 are then sliced to produce two pairs of binary value signals (
Φ1)
and (
Φ2). Each signal pair is fed to the input of a phase detector. The outputs of both
phase detectors are combined and low-pass ltered by LPF2 to produce signals dtd1 and
dtd2 as shown by equations Equation 3 and Equation 4.
(3)
(4)
Where Tp is the average period of s1 to s4, and D0 is an offset depending on the delay
parameter set by word DL[2:0] (D0 = DL/TP), via the I2C-bus, which is introduced to reduce
the sensitivity to noise. kDTD is the sensitivity of the phase detector (typically equal to 1)
and D(sx, sy) represents the delay time between signal sx and signal sy, given by:
if
where del(sx, sy) is the time delay between signal sx and signal sy; if signal sx leads
signal sy then del(sx, sy) > 0.
The difference between dtd1 and dtd2 (dtd1
dtd2) is multiplied with a drop-out
concealed normalization current IN and added to a xed offset current ID0. Two outputs are
produced which have an opposite sign in the modulation term, the polarity is specied by
bit DPOL. The possible values for the output signals are shown in Table 7.
Table 6:
DPD selection method
PD1
PD2
DTDC/I
S1
S2
S3
S4
0
VUA
VUB
VUC
VUD
0
1
0
VUA
VUD
VUC
VUB
1
0
VUA
VUB
VUA
VUB
1
0
VUA
VUD
VUA
VUD
X
1
VUA + VUC
VUB + VUD
VUA + VUC
VUB + VUD
dtd1
D
0
k
DTD
1
T
p
------
avg
×
Ds1 s2
,
() Ds3 s4
,
()
+
()
+
=
dtd2
D
0
k
DTD
1
T
p
------
avg
×
Ds2 s1
,
() Ds4 s3
,
()
+
()
+
=
Dsx sy
,
()
del sx sy
,
()
=
del sx sy
,
() 0
≥
Dsx sy
,
()
0
=
del sx sy
,
() 0
<
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