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參數(shù)資料
| 型號： | TZA3004HL |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 數(shù)字傳輸電路 |
| 英文描述： | SDH/SONET data and clock recovery unit STM1/4 OC3/12 |
| 中文描述： | CLOCK RECOVERY CIRCUIT, PQFP48 |
| 封裝： | 7 X 7 MM, 1.40 MM HEIGHT, PLASTIC, MS-026, SOT-313-2, LQFP-48 |
| 文件頁數(shù)： | 10/28頁 |
| 文件大小： | 127K |
| 代理商： | TZA3004HL |
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2000 Feb 17
10
Philips Semiconductors
Product specification
SDH/SONET STM1/OC3 and STM4/OC12
transceiver
TZA3005H
Reference clock (REFCLK and REFCLKQ)
These are differential PECL reference clock inputs for the
internal bit clock synthesizer.
Diagnostic loopback enable (DLEN)
This is an active-LOW TTL signal which selects diagnostic
loopback. When DLEN is HIGH, the TZA3005H receiver
usestheprimarydata(RXSD)andclock(RXSCLK)inputs.
When DLEN is LOW, the receiver uses the diagnostic
loopback clock and the transmitter input data.
Master reset (MRST)
This is an active LOW TTL signal which initializes the
transmitter. SYNCLKDIV is LOW during reset.
Line loopback enable (LLEN)
This is an active LOW TTL signal which selects line
loopback. When LLEN is LOW, the TZA3005H routes the
data and clock from the receiver inputs RXSD and
RXSCLK to the transmitter outputs TXSD and TXSCLK.
Reference select (REFSEL0 and REFSEL1)
These are TTL signals which select the reference clock
frequency (see Table 2).
Mode select (MODE)
This TTL signal selects the transmitter serial data rate.
MODE LOW selects 155.52 Mbits/s. MODE HIGH selects
622.08 Mbits/s.
Test inputs (ALTPIN, TEST1, TEST2, TEST3)
These are active HIGH TTL signals which control the
operating mode and test internal circuits during production
testing. For normal operation, these inputs are left
unconnected and internal pull-down resistors hold each
pin LOW. See Table 7 for more details.
T
RANSMITTER OUTPUT SIGNALS
Transmit clock outputs (TXSCLK and TXSCLKQ)
These are differential PECL serial clock signals which can
be used to retime TXSD. The clock frequency is either
155.52 MHz or 622.08 MHz depending on the operating
mode.
Transmit serial data (TXSD and TXSDQ)
These are differential PECL serial data stream outputs
which are normally connected to an optical transmitter
module or to the TZA3001 laser driver.
Parallel clock (SYNCLKDIV)
This is a TTL reference clock generated by dividing the
internal bit clock by eight, or by four when BUSWIDTH is
LOW. It is normally used to coordinate byte-wide transfers
between upstream logic and the TZA3005H.
Lock detect (LOCKDET)
This is an active HIGH CMOS signal. When active, it
indicates that the transmit PLL is locked to the reference
clock input.
19 MHz clock output (19MHZO)
This is a 19 MHz CMOS clock from the clock synthesizer.
It can be connected to the reference clock input of an
external clock recovery unit, such as the TZA3004.
R
ECEIVER OUTPUT SIGNALS
Parallel data outputs (RXPD0 to RXPD7)
These outputs comprise a parallel TTL data bus.
The parallel output data is aligned with the parallel output
clock (RXPCLK). RXPD7 is the most significant bit
(corresponding to bit 1 of each PCM word, the first bit
received). RXPD0 is the least significant bit
(corresponding to bit 8 of each PCM word, the last bit
received). RXPD0 to RXPD7 are updated on the falling
edge of RXPCLK. When a 4-bit bus width is selected,
RXPD7 is the most significant bit and bit 4 is the least
significant bit. Outputs RXPD0 to RXPD3 are forced LOW.
Frame pulse (FP)
This is a TTL signal which indicates frame boundaries
detected in the incoming data stream on pin RXSD. When
frame pattern detection is enabled (see Section
“Out-of-frame (OOF)”), FP goes HIGH for one cycle of
RXPCLK when a 48-bit sequence matching the frame
pattern is detected on inputs RXSD and RXSDQ. When
frame pattern detection is disabled, FP goes HIGH only
whentheincomingdatamatchestheframepattern andfits
exactly within the fixed byte boundary. FP is updated on
the falling edge of RXPCLK.
Parallel output clock (RXPCLK)
This is a TTL byte-rate output clock having a frequency of
either19.44,38.88,77.76 or 155.52 MHzandadutyfactor
of nominally 50%, to which the byte-serial output data bits
RXPD0 to RXPD7 are aligned. The falling edge of
RXPCLK updates the data on pins RXPD0 to RXPD7 and
the FP signal.
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| TZA3005 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:SDH/SONET STM1/OC3 and STM4/OC12 transceiver |
| TZA3005H | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:SDH/SONET STM1/OC3 and STM4/OC12 transceiver |
| TZA3011A | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:30 Mbits/s up to 3.2 Gbits/s A-rate(TM) laser drivers |
| TZA3011AVH/C2,551 | 功能描述:激光驅(qū)動器 3.3V D-LOOP LASERDRVR DC-3.2GB RoHS:否 制造商:Micrel 數(shù)據(jù)速率:4.25 Gbps 工作電源電壓:3 V to 3.6 V 電源電流:80 mA 最大工作溫度:+ 85 C 封裝 / 箱體:QFN-16 封裝:Tube |
| TZA3011AVH/C2,557 | 功能描述:激光驅(qū)動器 3.3V D-LOOP LASERDRVR DC-3.2GB RoHS:否 制造商:Micrel 數(shù)據(jù)速率:4.25 Gbps 工作電源電壓:3 V to 3.6 V 電源電流:80 mA 最大工作溫度:+ 85 C 封裝 / 箱體:QFN-16 封裝:Tube |
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