參數(shù)資料
型號(hào)： TZA3004HL
廠(chǎng)商： NXP SEMICONDUCTORS
元件分類(lèi)： 數(shù)字傳輸電路
英文描述： SDH/SONET data and clock recovery unit STM1/4 OC3/12
中文描述： CLOCK RECOVERY CIRCUIT, PQFP48
封裝： 7 X 7 MM, 1.40 MM HEIGHT, PLASTIC, MS-026, SOT-313-2, LQFP-48
文件頁(yè)數(shù)： 7/28頁(yè)
文件大?。?/td> 127K
代理商： TZA3004HL
2000 Feb 17
7
Philips Semiconductors
Product specification
SDH/SONET STM1/OC3 and STM4/OC12
transceiver
TZA3005H
FUNCTIONAL DESCRIPTION
Introduction
The TZA3005H transceiver implements SDH/SONET
serialization/deserialization, transmission and frame
detection/recovery functions. The TZA3005H can be used
as the front-end for SONET equipment. It handles the
serial receive and transmit interface functions including
parallel-to-serial and serial-to-parallel conversion and
clock generation. A block diagram showing the basic
operation of the chip is shown in Fig.1.
The TZA3005H has a transmitter section, a receiver
section, and an RF switch box. The sequence of
operations is as follows:
Transmitter operations:
– 4 or 8-bit parallel input
– parallel-to-serial conversion
– serial output.
Receiver operations:
– serial input
– frame detection
– serial-to-parallel conversion
– 4 or 8-bit parallel output.
The RF switch box receives serial clock and data signals
from the transmitter section, the receiver input buffers and
from the clock synthesizer. These signals are routed by
multiplexers to the transmitter section, the transmitter
output, the receiver and to the clock divider, depending on
the status of the control inputs. The switch box also
supports a number of test and loop modes.
Transmitter operation
The transmitter section of the TZA3005H converts
STM1/OC3 or STM4/OC12 byte-serial input data to a
bit-serial output data format. Input data rates of 19.44,
38.88, 77.76 or 155.52 Mbytes/s are converted to an
output data rate of either 155.52 or 622.08 Mbits/s. It also
provides diagnostic loopback (transmitter to receiver), line
loopback (receiver to transmitter) and also loop timing
(transmitter clocked by the receiver clock).
An integral frequency synthesizer, comprising a
phase-locked loop and a divider, can be used to generate
a high-frequency bit clock from an input reference clock
frequency of 19.44, 38.88, 51.84 or 77.76 MHz.
C
LOCK SYNTHESIZER
The clock synthesizer generates a serial output clock
(TXSCLK) which is phase synchronised with the input
reference clock (REFCLK). The serial output clock is
synthesized from one of four SDH/SONET input reference
clock frequencies and can have a frequency of either
155.52 MHz for STM1/OC3 or 622.08 MHz for
STM4/OC12 selected by the MODE input (see Table 1).
Table 1
Transmitter output clock (TXSCLK)
frequency options
The frequency of the input reference clock is divided to
obtain a frequency of about 19 MHz which is fed to the
phase detector in the PLL. The appropriate divisor is
selected by control inputs REFSEL0 and REFSEL1 as
shown in Table 2.
Table 2
Reference frequency (REFCLK) options
To ensure the TXSCLK frequency is accurate enough to
operate in a SONET system, REFCLK must be generated
from a differential PECL crystal oscillator having a
frequency accuracy better than 4.6 ppm for compliance
with “ITU G.813 (option 1)” or 20 ppm for “ITU G.813
(option 2)”
To comply with SONET jitter requirements, the maximum
value specified for reference clock signal jitter must be
guaranteed over the 12 kHz to 1 MHz bandwidth (see
Table 3).
MODE
INPUT
TXSCLK
FREQUENCY
OPERATING
MODE
0
1
155.52 MHz
622.08 MHz
STM1/OC3
STM4/OC12
REFSEL1
REFSEL0
REFCLK
FREQUENCY
0
0
1
1
0
1
0
1
19.44 MHz
38.88 MHz
51.84 MHz
77.76 MHz
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相關(guān)代理商/技術(shù)參數(shù)
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