參數(shù)資料
型號: UCC28517NE4
廠商: Texas Instruments, Inc.
元件分類: 基準(zhǔn)電壓源/電流源
英文描述: ADVANCED PFC/PWM COMBINA CONTROLLERS
中文描述: 高級式PFC /脈寬調(diào)制COMBINA控制器
文件頁數(shù): 15/39頁
文件大?。?/td> 725K
代理商: UCC28517NE4
SLUS517B DECEMBER 2002 REVISED AUGUST 2004
15
www.ti.com
APPLICATION INFORMATION
Select the regulation constant, k
1R
, of the energy storage voltage, as described by equation 2.
k
1R
0.29 for UCC28510, UCC28511, UCC28514, UCC28515
0.53 for UCC28512, UCC28513, UCC28516, UCC28517
There are effectively two options for k
1R
that directly relate to the two PWM hysteresis options, k
1R
= 0.29 and
k
1R
= 0.53. Select the large PWM hysteresis option if the system load has large, sudden step changes during
steady state operation. Select the small PWM hysteresis option if the system load has moderate step changes
or slow load changes during steady state operation. The PWM stage can be optimized best with the small PWM
hysteresis range because the maximum primary current of transformer T1 (which occurs at minimum V
C1
) is
smallest with the small PWM hysteresis range.
Select an approximate switching frequency for the PFC stage. A good starting frequency for a MOSFET based
PFC stage is in the range of 100 kHz to 200 kHz, depending on maximum line voltage and maximum line current.
Adjustments in switching frequency may result from meeting switching loss requirements in Q1 and D3, or in
order to optimize the design of L1.
Select an appropriate topology for the PWM stage using the information about the power requirements and the
magnitude of V
C1
. For simplicity, the typical application in Figure 1 shows a flyback converter in the PWM stage.
In most cases, the PWM stage topology must have transformer isolation and the topology must require only one
pulse-width signal. Topologies that have these features include:
single-transistor forward converter
single-transistor flyback converter
two-transistor forward converter
two-transistor flyback converter
Estimate the nominal and the maximum duty ratios of the PWM stage (D
2(nom)
, D
2(max)
and the associated peak
Q2 drain current, i
Q2(peak)
), based on the topology, PWM hysteresis option and output voltage requirements of
the PWM stage. Also estimate whether or not it is appropriate to operate the PWM stage at the same switching
frequency as the PFC stage or if the PWM stage can operate at twice the switching frequency of the PFC stage.
Base the estimation for the switching frequency of the PWM stage on the maximum voltages and currents of
the power MOSFETs and power diodes. Program the oscillator frequency of the PWM stage with the value of
R20.
R20
1
31
10
12
1 Hz
f
S(pwm)
2.0
10
7
Most applications require that the PWM stage regulates at the minimum energy storage capacitance voltage.
Maximum duty ratio D
2(max)
and i
Q2(peak)
should be calculated for the minimum energy storage voltage in order
to estimate the peak current stresses for transformer T1 and any other inductive element in the PWM stage.
V
C1(min)
1
k
1R
V
C1(nom)
At this point, enough information is available to estimate which member of the UCC28510 family should be
selected.
(2)
(3)
(4)
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