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參數(shù)資料
| 型號(hào)： | UCD7201RSA |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | Digital Control Compatible Dual Low-Side ? Amp MOSFET Drivers with Programmable Common Current Sense |
| 中文描述： | 數(shù)字控制兼容雙低邊？放大器MOSFET驅(qū)動(dòng)器，具有可編程通用電流檢測(cè) |
| 文件頁(yè)數(shù)： | 4/20頁(yè) |
| 文件大小： | 405K |
| 代理商： | UCD7201RSA |
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www.ti.com
UCD7201
SLUS645B–FEBRUARY 2005–REVISED JULY 2005
ELECTRICAL CHARACTERISTICS (continued)
V
DD
= 12 V, 4.7-μF capacitor from V
DD
to GND, 0.22
μ
F from 3V3 to AGND, T
A
= T
J
= -40°C to 105°C, (unless otherwise
noted).
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
MHz
Frequency
CURRENT LIMIT (ILIM)
ILIM internal current limit threshold
ILIM maximum current limit threshold
ILIM current limit threshold
ILIM minimum current limit threshold
CLF output high level
CLF output low level
Propagation delay from IN to CLF
CURRENT SENSE COMPARATOR
Bias voltage
Input bias current
Propagation delay from CS to OUTx
(1)
-
-
2
ILIM = OPEN
I
LIM
= 3.3 V
I
LIM
= 0.75 V
I
LIM
= 0.25 V
CS > I
LIM
, I
LOAD
= -7 mA
CS
≤
I
LIM
, I
LOAD
= 7 mA
IN rising to CLF falling after a current limit event
0.51
1.05
0.700
0.21
2.64
0.55
1.10
0.725
0.23
0.58
1.15
0.750
0.25
V
-
-
-
-
-
0.66
20
10
ns
Includes CS comp offset
5
-
25
–1
50
mV
uA
-
I
LIM
= 0.5 V, measured on OUTx, CS = threshold + 60 mV
-
25
40
ns
Propagation delay from CS to CLF
(1)
CURRENT SENSE DISCHARGE TRANSISTOR
Discharge resistance
OUTPUT DRIVERS
Source current
(1)
Sink current
(1)
Source current
(1)
Sink current
(1)
Rise time, t
R
Fall time, t
F
Output with VDD < UVLO
Propagation delay from IN to OUT1,
t
D1
Propagation delay from IN to OUT2,
t
D2
I
LIM
= 0.5 V, measured on CLF, CS = threshold + 60 mV
-
25
50
IN = low, resistance from CS to AGND
10
35
75
VDD = 12 V, IN = high, OUTx = 5 V
VDD = 12 V, IN = low, OUTx = 5 V
VDD = 4.75 V, IN = high, OUTx = 0
VDD = 4.75 V, IN = low, OUTx = 4.75 V
C
LOAD
= 2.2 nF, VDD = 12 V
C
LOAD
= 2.2 nF, VDD = 12 V
VDD =1.0 V, I
SINK
= 10 mA
4
4
2
3
A
10
10
0.8
20
15
1.2
ns
V
C
LOAD
= 2.2 nF, VDD = 12 V, CLK rising
20
35
ns
C
LOAD
= 2.2 nF, VDD = 12 V, CLK falling
20
35
(1)
Ensured by design. Not 100% tested in production.
4
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