參數(shù)資料
型號(hào): UCD7201RSA
廠商: Texas Instruments, Inc.
英文描述: Digital Control Compatible Dual Low-Side ? Amp MOSFET Drivers with Programmable Common Current Sense
中文描述: 數(shù)字控制兼容雙低邊?放大器MOSFET驅(qū)動(dòng)器,具有可編程通用電流檢測
文件頁數(shù): 6/20頁
文件大?。?/td> 405K
代理商: UCD7201RSA
www.ti.com
TERMINAL FUNCTIONS
UCD7201
SLUS645B–FEBRUARY 2005–REVISED JULY 2005
UCD7201
PIN
NAME
I/O
FUNCTION
HTSSOP
-14 PIN #
1
QFN-16
PIN #
-
NC
-
No Connection
Regulated 3.3-V rail. The onboard linear voltage regulator is capable of sourcing up to 10 mA
of current. Place 0.22 μF of ceramic capacitance from this pin to ground.
The IN pin is a high impedance digital input capable of accepting 3.3-V logic level signals up
to 2 MHz. There is an internal Schmitt trigger comparator which isolates the internal circuitry
from any external noise.
Analog ground return.
The IN pin is a high impedance digital input capable of accepting 3.3-V logic level signals up
to 2 MHz. There is an internal Schmitt trigger comparator which isolates the internal circuitry
from any external noise.
Current limit flag. When the CS level is greater than the ILIM voltage minus 25 mV, the output
of the driver is forced low and the current limit flag (CLF) is set high. The CLF signal is
latched high until the device receives the next rising edge on the IN pin.
Current limit threshold set pin. The current limit threshold can be set to any value between
0.25 V and 1.0 V. The default value while open is 0.5 V.
Current sense pin. Fast current limit comparator connected to the CS pin is used to protect
the power stage by implementing cycle-by-cycle current limiting.
Power ground return. The pin should be connected very closely to the source of the power
MOSFET.
The high-current TrueDrive driver output.
The high-current TrueDrive driver output.
Supply pin provides power for the output drivers. It is not connected internally to the VDD
supply rail. The bypass capacitor for this pin should be returned to PGND.
Supply input pin to power the driver. The UCD7K devices accept an input range of 4.5 V to 15
V. Bypass the pin with at least 4.7 μF of capacitance, returned to AGND.
No Connection.
2
1
3V3
O
3
2
IN1
I
4
3
AGND
-
5
4
IN2
I
6
5
CLF
O
7
6
ILIM
I
8
7
CS
I
9
8, 9
PGND
-
10
11
10
11
OUT2
OUT1
O
O
12
12
PVDD
I
13
13
VDD
I
14, 15,
16
14
NC
-
6
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