參數(shù)資料
型號(hào)： UCD7230_07
廠商： Texas Instruments, Inc.
英文描述： Digital Control Compatible Synchronous Buck Gate Drivers with Current Sense Conditioning Amplifier
中文描述： 數(shù)字控制兼容同步降壓門(mén)驅(qū)動(dòng)器，電流調(diào)節(jié)放大器檢測(cè)
文件頁(yè)數(shù)： 10/33頁(yè)
文件大?。?/td> 874K
代理商： UCD7230_07
www.ti.com
APPLICATION INFORMATION
Introduction
The UCD7230 is a synchronous buck driver with peak-current limiting. It is a member of the UCD7K family of
digital compatible drivers suitable either for applications utilizing digital control techniques or analog applications
that require local fast peak current limit protection.
Supply Requirements
The UCD7230 operates on a supply range of 4.5 V to 15.5 V. The supply voltage should be applied to three
pins, PVDD, VDD, and CSBIAS. PVDD is the supply pin for the lower driver, and has the greatest current
demands. The supply connection to PVDD is also the point where an external Schottky diode provides current to
the high side flying driver. PVDD should be bypassed to PGND with a low ESR ceramic capacitor. In the same
fashion, the flying driver should be bypassed between BST and SW.
Reference / External Bias Supply
The UCD7230 includes a series pass regulator to provide a regulated 3.3 V at the 3V3 pin that can be used to
power other circuits such as the UCD91xx, a microcontroller or an ASIC. 3V3 can source 10 mA of current. For
normal operation, place a 0.22-
μ
F ceramic capacitor between 3V3 and AGND.
Control Inputs
IN and SRE are high impedance digital inputs designed for 3.3-V logic-level signals. They both have 100-k
pull-down resistors. Schmitt Trigger input stage design immunizes the internal circuitry from external noise. IN is
the command input for the upper driver, OUT1, and can function up to 2 MHz. SRE controls the function of the
lower driver, OUT2. When SRE is false (low), OUT2 is held low. When SRE is true, OUT2 is inverted from OUT1
with appropriate delays that preclude cross conduction in the Buck MOSFETs.
UCD7230
SLUS741C–NOVEMBER 2006–REVISED MARCH 2007
In systems using the UCD7230, the feedback loop is closed externally and the IN signal represents the PWM
information required to regulate the output voltage. The PWM signal may be implemented by either a digital or
analog controller.
The UCD7230 has two over-current protection features, one that limits the peak current in the high-side switch
and one that limits the output current. Both limits are individually programmable. The internal current sense
blanking enables ease of design with real-world signals. In addition to over current limit protection, current sense
signals can be conditioned by the on board amplifier for use by the system controller.
VDD and CSBIAS are less demanding supply pins, and should be resistively coupled to the supply voltage for
isolation from noise generated by high current switching and parasitic board inductance. Use 33
for CSBIAS
and 1
for VDD. VDD should be bypassed to AGND with a 4.7-
μ
F ceramic capacitor while CSBIAS should be
bypassed to AGND with 0.1
μ
F. Although the three supply pins are not internally connected, they must be
biased to the same voltage. It is important that all bypassing be done with low parasitic inductance techniques to
good ground planes.
PGND and AGND are the ground return connections to the chip. Ground plane construction should be used for
both pins. For a MOSFET driver operating at high frequency, it is critical to minimize the stray inductance to
minimize overshoot, undershoot, and ringing. The low output impedance of the drivers produces waveforms with
high di/dt. This induces ringing in the parasitic inductances. It is highly desirable that the UCD7230 and the
MOSFETs be collocated. PGND and the AGND pins should be connected to the PowerPAD of the package
with two thin traces. It is critical to ensure that the voltage potential between these two pins does not exceed 0.3
V.
Although quiescent VDD current is low, total supply current depends on the gate drive output current required for
the capacitive load and the switching frequency. Total supply current is the sum of quiescent VDD current and
the average OUT current. Knowing the operating frequency and the MOSFET gate charge (Qg), average OUT
current can be calculated from (I
OUT
= Qg x f), where f is the operating frequency.
10
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
UCD7230A 制造商:TI 制造商全稱(chēng):Texas Instruments 功能描述:Digital Control Compatible Synchronous Buck Gate Driver with Current Sense Conditioning Amplifier
UCD7230ARGWR 功能描述:功率驅(qū)動(dòng)器IC Dig Pwr Comp Synch Buck Driver RoHS:否 制造商:Micrel 產(chǎn)品:MOSFET Gate Drivers 類(lèi)型:Low Cost High or Low Side MOSFET Driver 上升時(shí)間: 下降時(shí)間: 電源電壓-最大:30 V 電源電壓-最小:2.75 V 電源電流: 最大功率耗散: 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:SOIC-8 封裝:Tube
UCD7230ARGWT 功能描述:功率驅(qū)動(dòng)器IC Dig Pwr Comp Synch Buck Driver RoHS:否 制造商:Micrel 產(chǎn)品:MOSFET Gate Drivers 類(lèi)型:Low Cost High or Low Side MOSFET Driver 上升時(shí)間: 下降時(shí)間: 電源電壓-最大:30 V 電源電壓-最小:2.75 V 電源電流: 最大功率耗散: 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:SOIC-8 封裝:Tube
UCD7230PWP 功能描述:DC/DC 開(kāi)關(guān)控制器 Dig Pwr Comp Synch Buck RoHS:否 制造商:Texas Instruments 輸入電壓:6 V to 100 V 開(kāi)關(guān)頻率: 輸出電壓:1.215 V to 80 V 輸出電流:3.5 A 輸出端數(shù)量:1 最大工作溫度:+ 125 C 安裝風(fēng)格: 封裝 / 箱體:CPAK
UCD7230PWPG4 功能描述:DC/DC 開(kāi)關(guān)控制器 Dig Pwr Comp Synch Buck Drvr RoHS:否 制造商:Texas Instruments 輸入電壓:6 V to 100 V 開(kāi)關(guān)頻率: 輸出電壓:1.215 V to 80 V 輸出電流:3.5 A 輸出端數(shù)量:1 最大工作溫度:+ 125 C 安裝風(fēng)格: 封裝 / 箱體:CPAK
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