參數(shù)資料
型號(hào): UCD7230RGW
廠商: Texas Instruments, Inc.
英文描述: Digital Control Compatible Synchronous Buck Gate Drivers with Current Sense Conditioning Amplifier
中文描述: 數(shù)字控制兼容同步降壓門驅(qū)動(dòng)器,電流調(diào)節(jié)放大器檢測(cè)
文件頁(yè)數(shù): 6/33頁(yè)
文件大?。?/td> 874K
代理商: UCD7230RGW
www.ti.com
ELECTRICAL CHARACTERISTICS
V
DD
= P
VDD
= 12 V, 4.7-
μ
F from V
DD
to A
GND
, 1
μ
F from P
VDD
to P
GND
, 0.1
μ
F from CSBIAS to AGND, 0.22
μ
F from BST to
SW, T
A
= T
J
= -40°C to +125°C, R
CS+
= 5 k
, R
DLY
= 50 k
over operating free-air temperature range (unless otherwise
noted).
UCD7230
SLUS741C–NOVEMBER 2006–REVISED MARCH 2007
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
SUPPLY
Supply current, off
Supply current
V
DD
= 4.2 V
Outputs not switching IN = LOW
500
700
μ
A
mA
5
8
LOW-VOLTAGE UNDER-VOLTAGE LOCKOUT
VDD UVLO ON
VDD UVLO OFF
VDD UVLO hysteresis
REFERENCE / EXTERNAL BIAS SUPPLY
3V3 initial set point
3V3 over temperature
3V3 load regulation
V
DD
rising
V
DD
falling
4.25
4.00
100
4.50
4.25
250
4.75
4.50
400
V
mV
T
A
= 25
°
C
3.267
3.234
3.3
3.3
3.333
3.366
V
I
LOAD
= 1 mA to 10 mA, V
DD
= 5V
V
DD
= 4.75 V to 12 V, I
LOAD
= 10
mA
V
DD
= 4.75 V to 12 V
3.3 V rising
3.3 V falling
1
7
mV
3V3 line regulation
3
10
Short circuit current
3V3 OK threshold, ON
3V3 OK threshold, OFF
11
2.8
2.6
20
mA
3
3.2
3.0
V
2.8
INPUT SIGNAL (IN)
Positive-going input threshold
voltage
Negative-going input threshold
voltage
INHigh
1.6
1.9
2.2
INLow
1.0
1.3
1.6
V
INHigh –
INLow
Input voltage hysteresis
0.4
0.6
0.8
Input resistance to AGND
Frequency ceiling
CURRENT LIMIT (ILIM)
ILIM internal voltage setpoint
ILIM input impedance
CLF output high level
CLF output low level
Propagation delay from IN to reset
CLF
CURRENT SENSE COMPARATOR (OUTPUT SENSE)
50
100
150
k
MHz
2
I
LIM
=OPEN
0.47
20
2.7
0.50
42
0.53
65
V
k
I
LOAD
= 4 mA
I
LOAD
= 4 mA
2nd IN rising to CLF falling after a
current limit event
V
0.6
15
35
ns
I
LIM
= open
I
LIM
= 3.3 V
I
LIM
= 0.75 V
I
LIM
= 0.25 V
40
80
60
15
50
100
75
25
60
120
90
35
CS threshold (POS - NEG)
mV
Propagation delay from POS to
OUT1 falling
(1)
Propagation delay from POS to
CLF
(1)
I
LIM
= open, CS = threshold + 60 mV
90
ns
I
LIM
= open, CS = threshold + 60 mV
100
(1)
As designed and characterized. Not 100% tested in production.
6
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