2001
MOS FIELD EFFECT TRANSISTOR
μ
PA2750GR
SWITCHING
N-CHANNEL POWER MOS FET
DATA SHEET
Document No.
Date Published
Printed in Japan
G15780EJ1V0DS00 (1st edition)
March 2002 NS CP(K)
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all devices/types available in every country. Please check with local NEC representative for
availability and additional information.
PACKAGE DRAWING (Unit: mm)
1.27
0.12 M
6.0 ±0.3
4.4
0.40
+0.10
0.78 Max.
0
1
1
0.8
0.5 ±0.2
0
+
–
5.37 Max.
0.10
1
4
8
5
1
2
7, 8
3
4
5, 6
; Source 1
; Gate 1
; Drain 1
; Source 2
; Gate 2
; Drain 2
EQUIVALENT CIRCUIT
(1/2 circuit)
Source
Body
Diode
Gate
Protection
Diode
Gate
Drain
DESCRIPTION
The
μ
PA2750GR is N-Channel MOS Field Effect Transistor
designed for DC/DC converters and power management
application of notebook computers.
FEATURES
Dual chip type
Low on-state resistance
R
DS(on)1
= 15.5 m
MAX. (V
GS
= 10 V, I
D
= 4.5 A)
R
DS(on)2
= 21.0 m
MAX. (V
GS
= 4.5 V, I
D
= 4.5 A)
R
DS(on)3
= 23.9 m
MAX. (V
GS
= 4.0 V, I
D
= 4.5 A)
Low C
iss
: C
iss
= 1040 pF TYP. (V
DS
= 10 V, V
GS
= 0 V)
Built-in G-S protection diode
Small and surface mount package (Power SOP8)
ORDERING INFORMATION
PART NUMBER
μ
PA2750GR
PACKAGE
Power SOP8
ABSOLUTE MAXIMUM RATINGS (T
A
= 25°C, All terminals are connected.)
Drain to Source Voltage (V
GS
= 0 V)
V
DSS
30
V
Gate to Source Voltage (V
DS
= 0 V)
V
GSS
±20
V
Drain Current (DC)
Drain Current (pulse)
Note1
Total Power Dissipation (1 unit)
Note2
Total Power Dissipation (2 unit)
Note2
I
D(DC)
±9.0
A
I
D(pulse)
±36
A
P
T
1.7
W
P
T
2.0
W
Channel Temperature
T
ch
150
°C
Storage Temperature
Single Avalanche Current
Note3
Single Avalanche Energy
Note3
T
stg
–55 to +150
°C
I
AS
9.0
A
E
AS
8.1
mJ
Notes 1.
PW
≤
10
μ
s, Duty cycle
≤
1%
2.
T
A
= 25°C, Mounted on ceramic substrate of 2000 mm
2
x 2.2 mm
3.
Starting T
ch
= 25°C, V
DD
= 15 V, R
G
= 25
, V
GS
= 20
→
0 V
Remark
The diode connected between the gate and source of the transistor serves as a protector against ESD. When
this device actually used, an additional protection circuit is externally required if a voltage exceeding the rated
voltage may be applied to this device.