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參數資料
| 型號： | UPD17147GTA1 |
| 廠商： | NEC Corp. |
| 英文描述： | SMALL, GENERAL-PURPOSE 4-BIT SINGLE-CHIP MICROCONTROLLERS |
| 中文描述： | 小，通用4位單晶片微控制器 |
| 文件頁數： | 34/102頁 |
| 文件大?。?/td> | 408K |
| 代理商： | UPD17147GTA1 |
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34
μ
PD17145(A1), 17147(A1), 17149(A1)
Table 11-5. Read Contents of Port Register (0.73H)
Port Mode
Read Contents of Port Register (0.73H)
Input port
Pin status
Output port
Contents of output latch
Internal clock selected as serial clock
Contents of output latch
External clock selected as serial clock
Pin status
SI
Pin status
SO
Contents of output latch
TM1OUT
Contents of output latch
11.5 Port 0E (P0E
0
, P0E
1
, P0E
2
, P0E
3
)
Port 0E is a 4-bit I/O port with an output latch. It is mapped at address 6EH of BANK0 of the data memory.
The output format is N-ch open-drain output.
This port can be set in the input or output mode in 4-bit units. The input or output mode is specified by P0EGIO
(bit 2 of address 2CH) on the register file.
When P0EGIO = 0, all the pins of port 0E are set in the input mode. When an instruction that reads the data
of the port register is executed at this time, the pin status is read.
When P0EGIO = 1, all the pins of port 0E are set in the output port, and the contents written to the output
latch are output to the pins. When an instruction that reads the port status is executed with the port set in the
output mode, the contents of the output latch, instead of the pin status, are read.
A pull-up resistor can be connected on-chip to this port through software. Whether the pull-up resistor is
connected is specified by P0EGPU (bit 2 at address 0CH) of the register file. All the four-bit pins are pulled
up when P0EGPU = 1. When P0EGPU = 0, the pull-up resistor is not connected.
P0EGIO is cleared to “0” at reset, and all the P0E pins are set in the input mode. The value of the output
latch is also cleared to “0”.
Table 11-6. Writing and Reading Port Register (0.6EH)
(n = 0 to 3)
P0EGIO
Input/Output
BANK0 6EH
RF: 2CH, bit 2
Mode of Pin
Write
Read
0
Input
Enabled
P0E pin status
1
Output
Write to P0E latch
P0E latch contents
11.6 Port 0F (P0F
0
/RLS, P0F
1
/V
REF
)
Port 0F is a 2-bit input port and mapped at address 6FH of BANK0 of the data memory. A pull-up resistor
can be connected on-chip bitwise to this port by mask option.
If a read instruction that reads the port register is executed when both pins of port 0F are used as input port
pins, the higher 2 bits of the register are fixed to 0, and the pin statuses are read to the lower 2 bits. Executing
a write instruction is meaningless as the contents of the port register remain unchanged.
The P0F
0
/RLS pin is also used to input a standby mode release signal.
The P0F
1
/V
REF
pin inputs a reference voltage to the A/D converter when even one of the bits of P0CnIDI (RF:
address 1BH, n = 0 to 3) is set to “1”. If an instruction is executed to read the port register when the P0F
1
/V
REF
pin functions as the V
REF
pin, bit 1 of address 6FH is always cleared to 0.
SCK
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