參數(shù)資料
型號: UPD17245MC-xxx-5A4
廠商: NEC Corp.
英文描述: 4-BIT SINGLE-CHIP MICROCONTROLLERS FOR SMALL GENERAL-PURPOSE INFRARED REMOTE CONTROL TRANSMITTERS
中文描述: 4位單片微控制器的小型通用兩用紅外遙控遞質(zhì)
文件頁數(shù): 68/102頁
文件大?。?/td> 461K
代理商: UPD17245MC-XXX-5A4
68
Data Sheet U15002EJ1V0DS
μ
PD17240, 17241, 17242, 17243, 17244, 17245, 17246
9.
STANDBY FUNCTIONS
The
μ
PD17246 is provided with HALT and STOP modes as standby functions.
By using the standby function, current consumption can be reduced.
In the HALT mode, the program is not executed, but the system clock f
X
is not stopped. This mode is maintained,
until the HALT mode release condition is satisfied.
In the STOP mode, the system clock is stopped and program execution is stopped. This mode is maintained, until
the STOP mode release condition is satisfied.
The HALT mode is set, when the HALT instruction has been executed. The STOP mode is set, when the STOP
instruction has been executed.
9.1
HALT Mode
In this mode, program execution is temporarily stopped, with the main clock continuing oscillation, to reduce current
consumption.
Use the HALT instruction to set the HALT mode.
The HALT mode release condition can be specified by the operand for the HALT instruction, as shown in Table
9-1.
After the HALT mode has been released, the operation is performed as shown in Table 9-2 and Figure 9-1.
Caution Do not execute an instruction that clears the interrupt request flag (IRQ
×××
) for which the
interrupt enable flag (IP
×××
) is set immediately before the HALT 8H instruction; otherwise, the
HALT mode may not be set.
Table 9-1. HALT Mode Releasing Conditions
Operand Value
Release Conditions
0010B (02H)
When interrupt request (IRQTM) occurs for 8-bit timer
1000B (08H)
<1> When interrupt request (IRQTM, IRQBTM, or IRQ), whose interrupt enable flag (IPTM,
IPBTM, or IP) is set, occurs
<2> When any of P0A
0
to P0A
3
pins goes low
<3> When P0B
0
to P0B
3
, P0C
0
to P0C
3
, and P0D
0
to P0D
3
are used as input pins and any of these
goes low
<4> If P0E
0
to P0E
3
are used as input pins when a key matrix is used and if any of these pins goes
low
<5> If P1A
0
to P1A
2
and P1B
0
are used as input pins when a key matrix is used and if the level of any
of these pins is the set clear level
Note
Other than above
Setting prohibited
Note
Set the clear level by using bits 0 to 2 (P1AHL0 to P1AHL2) of the register file at address 05H, and bit 2
(P1BHL0) at address 15H.
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