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| 型號： | UPD17246MC-xxx-5A4 |
| 廠商： | NEC Corp. |
| 英文描述： | 4-BIT SINGLE-CHIP MICROCONTROLLERS FOR SMALL GENERAL-PURPOSE INFRARED REMOTE CONTROL TRANSMITTERS |
| 中文描述： | 4位單片微控制器的小型通用兩用紅外遙控遞質(zhì) |
| 文件頁數(shù)： | 4/102頁 |
| 文件大?。?/td> | 461K |
| 代理商： | UPD17246MC-XXX-5A4 |
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4
Data Sheet U15002EJ1V0DS
μ
PD17240, 17241, 17242, 17243, 17244, 17245, 17246
DIFFERENCES BETWEEN
μ
PD17246 SUBSERIES,
μ
PD17236 SUBSERIES, AND
μ
PD17255
SUBSERIES (2/2)
Item
μ
PD17246 Subseries
μ
PD17236 Subseries
μ
PD17225 Subseries
STOP mode release
condition
<1> When any of pins P0A
0
to P0A
3
goes low
<2> When pins P0B
0
to P0B
3
,
P0C
0
to P0C
3
, and P0D
0
to P0D
3
are used as input
pins and when any of
them goes low
<3> When an interrupt
request (IRQ) of the
interrupt for which the IP
flag is set is generated at
the rising edge or falling
edge of the INT pin
<4> When P0E
0
to P0E
3
are
used as input pins when
a key matrix is used and
when any of these pins
goes low
<5> When P1A
0
to P1A
2
and
P1B
0
are used as input
pins when a key matrix is
used and when the level
of any of these pins
equals the set clear level
<1> When any of pins P0A
0
to P0A
3
goes low
<2> When pins P0B
0
to P0B
3
, low
P0C
0
to P0C
3
, and P0D
0
to P0D
3
are used as
input pins and when any
of them goes low
<3> When an interrupt
request (IRQ) of the
interrupt for which the IP
flag is set is generated
at the rising edge or
falling edge of the INT
pin
When any of pins P0A
0
to
P0A
3
and P0B
0
to P0B
3
goes
Carrier frequency
(f
X
= 4 MHz)
Selected by register file
(after reset: f
X
/2)
<1> If carrier generation clock
is f
X
/2: 3.9 kHz to 1 MHz
<2> If carrier generation clock
is f
X
: 7.8 kHz to 2 MHz
<3> If carrier generation clock
is 2f
X
: 15.6 kHz to 4 MHz
Selected by mask option
<1> If carrier generation
clock is f
X
/2: 7.8 kHz to
1 MHz
<2> If carrier generation
clock is f
X
: 15.6 kHz to
2 MHz
7.8 kHz to 1 MHz
NRZ low-level period
setting modulo register
(NRZLTMM) and NRZ
high-level period setting
modulo register
NRZLTMM: 8 bits
(REM output control bit is bit
1 of register file at address
12H)
NRZHTMM: 8 bits
NRZLTMM: 7 bits (bit 7 is REM output control bit)
NRZHTMM: 7 bits (bit 7 is fixed to 0)
(NRZHTMM)
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