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參數(shù)資料
| 型號： | UPD17246MC-xxx-5A4 |
| 廠商： | NEC Corp. |
| 英文描述： | 4-BIT SINGLE-CHIP MICROCONTROLLERS FOR SMALL GENERAL-PURPOSE INFRARED REMOTE CONTROL TRANSMITTERS |
| 中文描述： | 4位單片微控制器的小型通用兩用紅外遙控遞質(zhì) |
| 文件頁數(shù)： | 73/102頁 |
| 文件大?。?/td> | 461K |
| 代理商： | UPD17246MC-XXX-5A4 |
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73
Data Sheet U15002EJ1V0DS
μ
PD17240, 17241, 17242, 17243, 17244, 17245, 17246
10. RESET
10.1 Reset by Reset Signal Input
When a low-level signal of more than 10
μ
s is input to the RESET pin, the
μ
PD17246 is reset.
When the system is reset, the oscillator remains in the HALT mode and then enters an operation mode, in the same
way as when the STOP mode is released. The wait time after the reset signal has been canceled is 16.384 ms (f
X
= 4 MHz).
On power application, input the reset signal at least once because the internal circuitry operations are not stable.
When
μ
PD17246 is reset, the following initialization takes place.
(1) Program counter is reset to 0.
(2) Flags in the register file are initialized to their default values (for the default values, refer to
Figure 12-1
Register Files
).
(3) The default value (0320H) is written to the data buffer (DBF).
(4) The hardware peripherals are initialized.
(5) The system clock (f
X
) stops oscillation.
When the RESET pin is made high, the system clock starts oscillating, and the program execution starts from
address 0 about 16 ms (at 4 MHz) later.
Figure 10-1. Reset Operation by RESET Input
RESET
Wait
Starts from address 0H
(about 16 ms at 4 MHz)
Operation mode
or standby mode
HALT mode
Operation mode
Oscillation stops
10.2 Reset by Watchdog Timer (with RESET Pin Internally Pulled Down)
When the watchdog timer operates during program execution, the RESET pin is internally pulled down, and the
program counter is reset to 0 (normally, the RESET pin is pulled up).
If the watchdog timer is not reset for a fixed period of time, the program can be restarted from address 0H.
Program so that the watchdog timer is reset at intervals of within 340 ms (at f
X
= 4 MHz) (set the WDTRES flag).
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