參數(shù)資料
型號(hào)： UPD1724x
廠商： NEC Corp.
英文描述： 4-BIT SINGLE-CHIP MICROCONTROLLERS FOR SMALL GENERAL-PURPOSE INFRARED REMOTE CONTROL TRANSMITTERS
中文描述： 4位單片微控制器的小型通用兩用紅外遙控遞質(zhì)
文件頁(yè)數(shù)： 69/102頁(yè)
文件大?。?/td> 461K
代理商： UPD1724X
69
Data Sheet U15002EJ1V0DS
μ
PD17240, 17241, 17242, 17243, 17244, 17245, 17246
Table 9-2. Operations After HALT Mode Release
(a) HALT 08H
HALT Mode Released by:
Interrupt Status
Interrupt Enable Flag
Operations After HALT Mode Release
When release condition of P0A
0
to P0A
3
,
P0B
0
to P0B
3
, P0C
0
to
P0C
3
, P0D
0
to P0D
3
, P0E
0
to P0E
3
,
P1A
0
to P1A
2
, P1B
0
is satisfied
Don’t care
Don’t care
Instruction next to HALT is executed
When release condition is
satisfied by interrupt request
DI
Disabled
Standby mode is not released
Enabled
Instruction next to HALT is executed
EI
Disabled
Standby mode is not released
Enabled
Branches to interrupt vector address
(b) HALT 02H
HALT Mode Released by:
Interrupt Status
Interrupt Enable Flag
Operations After HALT Mode Release
8-bit timer
DI
Disabled
Instructions are executed from the
instruction next to the HALT instruction.
Enabled
EI
Disabled
Enabled
Branches to interrupt vector address
9.2
HALT Instruction Execution Conditions
The HALT instruction can be executed under special conditions, as shown in Table 9-3, to prevent the program
from hanging up.
If the conditions in Table 9-3 are not satisfied, the HALT instruction is treated as a NOP instruction.
Table 9-3. HALT Instruction Execution Conditions
Operand Value
Execution Conditions
0010B (02H)
When all interrupt request flags (IRQTM) of 8-bit timer are reset
1000B (08H)
<1> When interrupt request flag (IRQTH, IRQBTM, or IRQ) is reset, corresponding to interrupt whose
interrupt enable flag (IPTM, IPBTM, or IP) is set
<2> When high level is input to all P0A
0
to P0A
3
pins
<3> When P0B
0
to P0B
3
, P0C
0
to P0C
3
, and P0D
0
to P0D
3
are used as input pins, a high level must
be input to all the pins.
<4> A high level must be input to all the pins if P0E
0
to P0E
3
are used as input pins when a key
matrix is used.
<5> A level reverse to the set clear level
Note
must be input to all the pins if P1A
0
to P1A
2
and P1B
0
are used as input pins when a key matrix is used (for example, if the clear level is high, the
execution condition is low-level input).
Other than above
Setting prohibited
Note
Set the clear level by using bits 0 to 2 (P1AHL0 to P1AHL2) of the register file at address 05H, and bit 2
(P1BHL0) at address 15H.
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